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Better debugging with the Visualizer Debug Environment
With post-processing analysis and debugging of data captured during runs of the Questa Advanced Simulator, Pixelworks improved the efficiency of its UVM-based verification flow. Read the success story
Mentor Design Areas
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. View Journal Article
- ASSET InterTech/Mentor Graphics DFT Technology Seminar ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarCambridge, UK • Mar 26, 2015 ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarMunich, Germany • Mar 27, 2015 ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarShenzhen, China • Apr 21, 2015
- DVCon 2015 DVCon 2015http://www.mentor.com/events/design-verificationSan Jose, CA • Mar 2, 2015
- FloEFD CAD Embedded CFD Hands On Workshop – at NIAR FloEFD CAD Embedded CFD Hands On Workshop – at NIARhttp://www.mentor.com/products/mechanical/events/niar-floefd-cad-embedded-cfd-hands-onWichita, KS • Mar 10, 2015