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Starting at 2pm: "DDR Interface and SerDes Channel Design for High Performance FPG-based PCBs" #DesignCon workshop Room 201/2nd Floor #DC15 | 28 Jan
The #DesignCon expo hall is now open! Make sure to stop by Mentor booth 935 to chat with our experts and view demonstrations. #DC15 | 28 Jan
RT @jhupcey: @mentor_graphics now: verification expert Mark Eslinger kicks off free seminar on eliminating unwanted 'X's #semieda http://t.… | 28 Jan
New white paper – "Reducing Cost and Risk with Effective Solder Joint Analysis During PCB Assembly." Download here: http://t.co/jB6O6hNoER | 28 Jan
Ariel Zauer presents a comprehensive approach to stackup and SI modeling during his #DesignCon workshop (10:15, Room 201/2nd Floor) #DC15 | 28 Jan
Our first #DesignCon workshop starts at 8:30am - "A Holistic Approach to IC, Package and Board Co-Optimization" (2nd floor/Room 201) | 28 Jan

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