Precision RTL Front-To-Back Design Flow
- Add Courses
- Confirm Schedule
- Enter Contact Information
There are currently no dates scheduled for this class. Request this class in your area!
Duration: 2 Days
Course Part Number: 217483
Description
Education Services can help you acquire the skills needed to customize Falcon FPGA Front-to-back Design Flow training is an intensive 2 day course. It combines a rapid introduction to the latest FPGA devices and the associated HDL design flow, including a detailed exploration of how to make the best use of Mentor Graphics® FPGA tools and with special focus on the new Precision Synthesis software.
All lab exercises in the course are presented within the context of Mentor Graphics FPGA Design tools. Exercises are designed to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. Students will gain experience in simulating VHDL or Verilog models with ModelSim, synthesizing designs with Precision Synthesis and implementing them using the FPGA vendors' place and route tools.
Objective
- Exploit the hardware features of FPGAs.
- Take advantage of the benefits of VHDL or Verilog without sacrificing device performance.
- Manage the complete programmable device design flow using VHDL or Verilog, from design entry through synthesis and place and route to back-annotation, timing analysis and device programming.
Audience
- Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog simulation and analysis for FPGAs.
Prerequisites
- A good working knowledge of how to write VHDL or Verilog for simulation and RTL synthesis. However, students will not be expected to write HDL code.
- Some previous experience with ModelSim, Precision Synthesis and Place and Route tools is helpful but not required.