VStation Training for HW designers

Duration:  2 Days
Course Part Number: 212619

Description

The heart of the VStation verification station is the VirtuaLogic Tool suite. Supporting both VHDL and Verilog, these tools offer fully integrated RTL compile and debug capabilities with a user-friendly, intuitive GUI. This course offers the knowledge and skills needed to import, verify and compile a design, then debug any problems that may occur during the process.

Detailed lab exercises help reinforce what you learned in the section topics.

You will learn how to

• Import an RTL design into the VStation emulation environment
• Create the required design and emulation control files
• Run, debug and optimize designs

Audience

Primarily VirtuaLogic users responsible for design preparation and compiling.

Prerequisites

• A basic knowledge of digital circuit design and function
• A basic knowledge of VHDL or Verilog
• A working knowledge of UNIX

Key Topics

• Emulation Introduction and System Overview
• Netlist Import and Technology Mapping
• Memory Specification
• Timing Specification
• Probing and 100% Visibility
• Running and debugging the design

Price: 1.200 EUR