VStation Training for SW Designers
- Add Courses
- Confirm Schedule
- Enter Contact Information
There are currently no dates scheduled for this class. Request this class in your area!
Duration: 1 Day
Course Part Number: 214251
Description
The heart of the VStation verification station is the VirtuaLogic Tool suite. Supporting both VHDL and Verilog, these tools offer fully integrated RTL compile and debug capabilities with a user-friendly, intuitive GUI. This course offers the knowledge and skills needed for SW designers to run succefully emulation runs and be able to debug the design.
You will learn how to
- Run and debug designs
- Run basic compiles
Audience
Primarily SW designers that are using emulation
Key Topics
- Emulation Introduction and System Overview
- Probing and 100% Visibility
- Running and debugging the design