Calibre Rule Writing
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| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Dec 09, 2008 | Dec 12, 2008 | 9:00am - 5:00pm | Espoo, FI | Register |
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Duration: 4days
Course Part Number: 058450
Description
This class will help you to maximize your usage of Calibre, the industry standard for deep submicron physical verification. The "Calibre Rule Writing" course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks.
The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.
You will learn how to
- Write various types of DRC rules dealing with the width, spacing, overlap, enclosure, and extension requirements for different layers in your semiconductor process
- Write rules to control DRC output
- Use Boolean and topological operators to derive layers and use layer modifiers to change layer size
- Debug rule files
- Use edge directed checks to derive edge layers
- Use error directed checking to detect discrepancies
- Write a variety of complex, special, DRC rules dealing with antenna checks, line-end checks, direction of current flow checks, density checks, and metal fills specified in your process document, using state-of-the-art verification techniques
- Write rules to establish layout connectivity
- Write rules to control how cell data is used during DRC
- Deal with specific issues in hierarchical DRC
- Write equation-based DRC rule checks
- Create and use layer properties
- Write rules to recognize different devices such as MOS transistors, resistors and capacitors of different types, bipolar transistors etc. in the layout
- Write rules to define your own custom devices
- Extract various properties such as width, length, resistance and capacitance of these recognized devices, using the Built-in property language within Calibre nmLVS TM and compare values in the source netlist
- Effectively utilize the text already present in the GDSII layout database, and to supplement it with text supplied through the rule file to annotate nets and ports
- Optimally use the various Calibre statements that deal with net and port names in the layout
- Write various LVS specification statements that control how the layout netlist extracted from the layout database is compared to the source netlist
- Effectively block out selected cells during the LVS Netlist comparison process
- Write rules to control how cell data is used during LVS
- Work with device signatures
- Call Calibre TVF routines from within device property computation functions
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Calibre under the guidance of our expert instructors. Hands-on lab topics include:
- Preparing the Rule File and Running Calibre
- Displaying the Layout and Viewing Results
- Editing a Variable
- Using the Online Documentation
- Preparing the Layer Definitions
- Preparing the Layout Specification Statements
- Determining the DRC Output Control Statements
- Creating and Running the Rule File
- Improving the Output Display
- Writing and Testing Dimensional Rule Checks
- Designing and Testing Derived Layer Statements
- Writing and Testing Dimensional Checks Using Derived Layers
- Writing Polygon-directed Rule Checks
- Designing and Testing Edge and Error-directed Rule Checks
- Creating and Using Layer Properties
- Writing and Testing Connectivity Statements
- Designing and Testing Antenna Rule Checks
- Writing Layout vs. Layout Rule Decks
- Taking Advantage of Hierarchy
- Determining the LVS Output Control Statements
- Setting LVS Report Options
- Debugging Shorts Using LVS Isolate Shorts
- Setting Ground and Source Names
- Finding Soft Connections
- Creating and Naming Ports
- Inserting Text Objects Into a Layout Using the Rule File
- Writing Device Recognition Statements
- Use the COPY Command to Assist in Troubleshooting/Developing Device Statements
- Specifying Custom User-Defined Devices
- Performing Off-Grid checking
- Using the Built-in language to Define Device Properties
- Using the Debugger to Troubleshoot Device Property Computations
Audience
- Experienced IC Layout Engineers and Layout Verification specialists who will write, maintain, support, and optimize various DRC and LVS rule decks in their organization
- Experienced CAD Engineers and Managers who will be responsible for integration of the Calibre toolset in their design flow
- Experienced CAD specialists who interface with various foundries (such as TSMC, UMC, Chartered) and integrate the rule decks supplied by these foundries into the verification flow
- Layout Verification specialists in foundries who are responsible for generating qualified rule decks for their various process offerings
Prerequisites
- Completion of the Calibre nmDRC/nmLVS class is very highly recommended
- Thorough knowledge of IC layout techniques and procedures
- Experience with an IC layout editing tool
- Good understanding of SPICE netlists
- Familiarity with UNIX
- Good understanding of layout verification concepts and experience with layout verification tools
Key Topics
- Calibre Basic Concepts
- DRC Basics
- Dimensional Rule Checks
- Polygon-Directed Rule Checks
- Edge and Error-Directed Rule Checks
- Net Area Ratio Command and Antenna checking
- Hierarchical Considerations and Dual Database Capabilities
- Writing DRC Rules Efficiently
- Writing Equation-Based DRC Rule Checks
- Working With Layer Properties
- Creating and Using Device Signatures
- Using Calibre TVF for Device Property Computation