ADVance MS for A/MS Design Verification
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Duration: 2 Days
Course Part Number: 217225
Course Overview
Education Services can help you acquire the skills needed to maximize your usage of ADVance MS and realize its full impact on your analog/mixed signal designs. You will study design flows and representations, in particular top-down design and bottom-up verification and how the tool may be used to bring a design to completion. You will be shown the advantages of behavioral modeling languages in verification, allowing you to verify your full design at transistor-level with easily replacing any behavioral description with its Spice equivalent.
YOU WILL LEARN HOW TO
- Use ADVance MS proficiently on large analog/mixed signal designs
- Compile text models written in VHDL, VHDL-AMS, Verilog and Verilog-AMS
- Set up, run, and interpret results
- Use EZwave to help you analyze your results
- Instantiate Spice subcircuits in a HDL design (HDL on top methodology)
- Instanciate HDL models in a Spice description (Spice on top methodology)
- Configure a Spice design
- Appropriately insert and configure boundary converters between analog and digital parts of your design
- Run full chip verification with ADMS ADiT
- Make effective use of advanced features and tips specific to your design methodology
HANDS-ON LABS
Throughout this course, extensive hands-on lab exercises provide you with practical experience using ADVance MS.
AUDIENCE
This course is intended for designers who want to be able to simulate analog, digital and mixed-signal parts all together, giving them the ability to design and verify a complete chip in the same simulation environment.
PREREQUISITES
- Familiarity with Unix operating systems
- Knowledge of principals of SPICE simulation
- Working knowledge of Hardware Description Languages (VHDL and/or Verilog)
- Familiarity with ModelSim® is a plus
- Practical experience with analog design and simulation is a plus
KEY TOPICS
Day 1
- Introduction to ADMS
- Library Management
- Running Mixed-Signal Simulations
- EZwave
Day 2
- HDL Instantiating Spice
- Spice instantiating HDL
- Spice Design Configuration
- Boundary Models
- ADMS ADiT
