Signal Integrity and High-speed Methodology
- Add Courses
- Confirm Schedule
- Enter Contact Information
| Date Begins | Date Ends | Time | Location | Register |
|---|---|---|---|---|
| Oct 13, 2008 | Oct 15, 2008 | 9:55am - 5:55pm | Espoo, FI | Register |
Don't see a date or location that works for you? Click here to request this class in your area!
Duration: 3 Days
Course Part Number: 207339
Description
Learn the methodology, techniques and processes that have enabled the World's foremost electronic design companies to pioneer leading edge designs. Signal Integrity and High Speed Methodology will teach you to make quality digital designs and printed circuit boards through knowledge of signal integrity.
The lecture modules address transmission lines and their effects on digital circuitry and printed circuit boards. Our industry expert instructor, Rod Strange, will lead you through detailed examples from real-world designs to demonstrate the necessity of understanding signal integrity issues and applying sound signal integrity principles to your designs. Specific tools are rarely discussed and therefore the class is appropriate for all Engineers involved in high speed digital pcb designs.
You will learn how to
- Understand transmission lines and their effect on digital circuitry
- Appreciate the importance of printed circuit boards: drivers, receivers, Zo, Zdiff, stackup
- Understand Quality board designs
- Explain Termination, topology,timing, parasitics, etc
- Understand Crosstalk:understanding and preventing
- Work with Differential pair:termination, routing, timing, EMI
- Understand Clock distribution,high speed busses, groundbounce
- Explain Reference planes:ground, power, return currents, splits
- Understand High speed layout:vias, connectors, capacitors, losses
- Discuss Testing issues:equipment, probes, test points
- Know Models: SPICE, IBIS, drivers,receivers, simulators and accuracy
- Do PCB simulations that detectsignal integrity problems before fabrication
Audience
- Digital Design Engineers
- ECAD Designers with some high speed experience
- Technicians with High Speed experience
- Those who would like to further their knowledge on Printed Circuit Board Signal Integrity issues.
Key Topics
What is a transmission line?
- What causes transmission lines?
- What do they do to digital circuitry?
- What can be done to avoid transmission lines?
Transmission line effects
- Undershoot
- Overshoot
- Ringback
- Monotonicity
- Crosstalk
- Timing
- Overshoot and undershoot can destroy boards
Reference return current
- Where does the return current flow
- How does it flow to the reference plane
Printed circuit boards
- Stackup
- How to make controlled Zo
- Controlled Zo or controlled distance
Drivers, receivers, Zo
- How strong should the drivers be?
- How fast should the drivers be?
- How many receivers can I have?
- What should the Zo be?
- Incident vs reflected wave switching
Board interconnect delay
- How is it different than system delay
- Need to include interconnect delay in timing
- How is it calculated
- Receiver input C
- Driver output Rs
- PCB Zo
- Reflected vs incident wave switching
Quality board designs
- What needs to be done to make quality boards?
- What tools are needed to make quality boards?
- Signal integrity issues must be included
Termination
- When is it needed
- Required to stop undershoot and overshoot
- Driver and topology dependent
- Placement and stub length
- Parallel
- Series
- AC parallel
- Zo matching
- Driving Rs matching
- Diode
Topologies
- When are topologies important
- How do topologies affect signal integrity
- How do topologies affect timing
- Driver and termination dependent
- Stub length
- Short Tee
- Long Tee
- Star
- Daisy chain
Parasitics
- L's, C's, and R's
- How do they affect the timing
- How do they affect signal integrity
- How to minimize their effects
- How capacitance affects Zo
Differential pair
- Why are they important
- Noise and EMI
- Layout issues
- Zdiff, Zcomm, Zeven, & Zodd
- Controlling Zdiff
- Side to side vs broadside
- Coupling issues
- Weak vs strong coupling
- Zdiff changes
- Skew affects on timing
- Skew affects on signal integrity
- Terminations
Crosstalk
- Very important with dense boards
- What causes crosstalk
- How can crosstalk be minimized
- What factors can be controlled
- Faster silicon then more crosstalk
- Routing densities
- What needs to be done by layout engineers
- Effects on timing
- Microstrip vs stripline
Groundbounce
- What causes groundbounce
- What does it do to driver voltage levels
- What does it do to receiver voltage levels
- How can I test for it
- How can I stop it
- Problems with FPGAs and ASICs
- Number of outputs switching possible
Bypass capacitors
- What physical size
- ESL & ESR
- Package vs inductance
- Placement
- PCB electrical mounting
- Loop inductance
Reference planes
- Perferation
- Crossing splits
- Consistency in designs
- Layer changes
- Vias and references
- Board to board consistency
Connectors
- Controlled Zo
- Geometry
- Pinouts
- Reference consistency
- Coupling
Vias & plated thru holes
- Zo changes
- Reference changes
- Stub lengths
- When are they important
- How to avoid vias issues
- Blind & buried vias
- Dimension affects on parasitics
- Pads, antipads, hole diameter
PCB's
- Stackup & references
- Reference control and consistency
AC losses
- Skin effect
- Dielectric loss
- Microstrip vs stripline
- Noise margins with differential pair
Layout issues
- Boards are becoming more difficult to layout
- What issues are important in todayâ|£8364;â„¢s fast boards
Testing issues
- Faster boards are harder to test
- How do you test them
- What equipment do you need
- How fast does the equipment need to be
- Many older methods no longer work
Models
- SPICE
- IBIS
- Drivers
- Receivers
- Simulators
- Accuracy
From paper at European High Speed Symposium in
Munich :
Crosstalk
- Forward & reverse
- Far-end & near-end
- Microstrip vs stripline
- Driver & receiver direction affects
- Parallel tracking
- Spacing
- Driver strength & speed
- Termination affects
- Noise margin
- Board layout
- Controlling and reducing
- How crosstalk changes timing
- Pattern dependent
From paper at User2User High Speed Seminar in San Jose: :
Split plane crossings
- Reference return current
- Signals crossing reference splits
- Microstrip vs Stripline
- Size of split
- Plane to plane spacing
- Timing
- Signal integrity
- Multiple signals crossing together
- How do splits affect crosstalk
- Vias and reference changes
- Board to board reference changes
- System considerations