Posted Feb 17, 2012, by Dennis Brophy
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More
Tags:
DATE Conference,
DVCon,
Accellera,
UVM,
SystemC
Posted Nov 10, 2011, by Dennis Brophy
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More
Tags:
SystemC,
TLM,
Accellera,
1666,
OVM,
TLM 1.0,
TLM 2.0,
UVM,
OSCI,
Verification Academy
Posted Oct 13, 2011, by Dennis Brophy
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, … Read More
Tags:
VHS,
Verification,
VIP-TSC,
betamax,
e,
Accellera,
UVM,
OVM
Posted Oct 5, 2011, by Dennis Brophy
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
Tags:
VMM,
VIP-TSC,
Accellera,
UVM,
OVM
Posted Jul 22, 2011, by Dennis Brophy
Historical Perspective
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and … Read More
Tags:
VITAL,
VHDL,
VMM,
OVM,
Accellera,
UVM,
UVM World,
OVM World
Posted Jun 21, 2011, by Dennis Brophy
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained … Read More
Tags:
SystemC,
TLM,
Accellera,
1666,
UVM,
OSCI,
DAC,
DATE
Posted Apr 21, 2011, by Dennis Brophy
User Adoption of OVM Featured; Views on UVM Discussed
The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set. U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens.
Registration for the event is open and is fee-free. U2U … Read More
Tags:
Functional Verification,
OVM,
Accellera,
UVM,
VIP,
U2U
Posted Feb 22, 2011, by J VanDomelen
The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs.
Accellera’s Verification IP (VIP) Technical … Read More
Tags:
UVM,
Universal Verification Methodology,
Milaero,
Design,
Design Automation,
Open Verification Methodology,
OVM,
TSC,
Accellera,
IC,
Mentor,
Mentor Graphics,
integrated circuit,
Mentor.com,
EDA,
Mil-Aero,
electronic design automation,
IP,
intellectual property,
John Lenyo,
Verification IP (VIP) Technical Subcommittee (TSC),
VIP
Posted Jan 28, 2011, by Dennis Brophy
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity
The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology. With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa.
The major addition to SCE-MI 2.1 is support … Read More
Tags:
UVM,
DVCon,
EDSFair,
Accellera,
OVM,
SCE-MI
Posted Oct 14, 2010, by Dennis Brophy
23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package
As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway. While the Accellera VIP-TSC is making good progress, limited information is available to non-participants. This limited knowledge is true for … Read More
Tags:
interoperability forum,
Register Package,
Accellera,
UVM,
VIP-TSC,
synopsys
Jim Martens
John Day
Nazita Saye
Michael Ford
Robin Bornoff
Mike Jensen
Colin Walls
Tom Fitzpatrick
Max Clark
Patrick Carrier
Mark Laing
Travis Mikjaniec
Chris Hallinan
Christopher Hallinan
Bernard Sutton