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Mentor Blogs

Posts tagged with 'Accellera'

25 Apr, 2014

Dennis Brophy DVCon 2014 Conference Proceedings Published With record attendance announced for DVCon 2014, one might wonder if there is really a need to put some of the “Accellera Day” tutorial videos online.  With more than 1,000 professionals attending in some capacity, it would be easy to conclude that everyone that needs to know about UVM and the developments on the updated version to it, probably know.  Looking … Read More

DVCon, Functional Verification, Accellera, UVM, register layer, stimulus generation

10 Apr, 2014

Dennis Brophy Its always fun to take the wraps off of solutions we have been hard at work developing.  The global team of Mentor Graphics engineers have spent considerable time and energy to bring the next level of SoC design and verification productivity to what seems to be a never ending response to Moore’s Law.  As silicon feature sizes get smaller, design sizes get larger and the verification problem mushrooms.  … Read More

UPF, UVM, Codelink, Enterprise Verification Platform, Accellera, Portable Stimulus, VirtuaLAB, Gary Smith EDA, Moore's Law

25 Feb, 2014

Dennis Brophy As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less? In DVCon’s recent past, it was a tradition for the North American SystemC User Group (NASCUG) to sponsor a day of activity before the official start of the conference.  When OSCI merged with Accellera, the day before the official conference start grew to become Accellera Day with a broader set … Read More

DVCon, Emulation, Accellera, SystemC, Formal Verification, fpga prototype

23 Feb, 2014

Dennis Brophy UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest.  It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon. The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of … Read More

DVClub, DVCon, Accellera, Universal Verification Methodology, UVM 1.2, Git, OSCI

6 Jan, 2014

Dennis Brophy The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification.  Two factors that are easy to measure is the time it takes to simulate a design and the other is the size of the dataset that contains the results of the verification runs. Simulation times are growing and the datasets are getting larger.  While time and attention is given to accelerated verification through … Read More

Coverage Closure, DVClub, Accellera, UCIS, Unified Coverage Interoperability Standard, Metrics

19 Sep, 2013

Dave Rich It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added Object-Oriented Programming features for testbench development to a language predominately used for RTL design synthesis. Making debug easier was one of the driving forces in unifying testbench and design features into a single language. The semantics for evaluating expressions and executing … Read More

Accellera, testbench, Verification

8 Sep, 2013

Harry Foster Schedules, respins, and bug classification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 11 click here), I focused on some of the 2012 Wilson Research Group findings related to formal verification, acceleration/emulation, and FPGA prototyping … Read More

IEEE 1800, Accellera

26 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

19 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

12 Aug, 2013

Harry Foster Language and Library Trends (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 8 click here), I focused on design and verification language trends, as identified by the Wilson Research Group study. This blog presents additional … Read More

SVA, UVM, Accellera, Assertion-Based Verification, Verification Methodology, OVL, PSL, Functional Verification

5 Aug, 2013

Harry Foster Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 7 click here), I focused on some of the 2012 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present … Read More

IEEE 1800, RTL, VHDL, 1364, testbench, Verification, Verification Academy, 1076, Verilog, Functional Verification, SystemC, Accellera, functional coverage

29 Jul, 2013

Harry Foster Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. In this blog, I focus on some of the 2012 Wilson Research Group … Read More

testbench, UVM, Accellera, Formal Verification, Verification, IEEE 1800, Functional Verification

22 Jul, 2013

Harry Foster Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues that discussion. I stated in my previous blog that … Read More

Verification Academy, Verification, Verification Methodology, Formal Verification, Functional Verification, Accellera, UVM, IEEE 1800

15 Jul, 2013

Harry Foster   Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of the amount of effort spent in verification. Directly asking study participants … Read More

Functional Verification, Accellera, Verification Academy, Verification Methodology, Verification

28 Jun, 2013

Harry Foster Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends. Independent Asynchronous Clock Domains Figure 1 shows the percentage … Read More

Verification Academy, Verification, Verification Methodology, Functional Verification, Accellera, Wilson Research Group Study, UPF, IEEE 1801, Low Power

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