Mentor Blogs

Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs.  The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011). Harry has been … Read More

VMM, VIP-TSC, Accellera, UVM, OVM

Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase.  New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it.  Everyone had their favorite VHDL book and … Read More

VITAL, VHDL, VMM, OVM, Accellera, UVM, UVM World, OVM World

System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here. While this may come as a surprise to many, one thing has remained … Read More

SystemC, TLM, Accellera, 1666, UVM, OSCI, DAC, DATE

User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free.  U2U … Read More

Functional Verification, OVM, Accellera, UVM, VIP, U2U

The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More

UVM, Universal Verification Methodology, Milaero, Design Automation, Open Verification Methodology, OVM, TSC, Accellera, IC, Mentor, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for … Read More

interoperability forum, Register Package, Accellera, UVM, VIP-TSC, synopsys

Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC).  Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate. As … Read More

OVM, ral, Accellera, UVM, VIP-TSC

Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently. Further, as part of the Accellera VIP-TSC UVM development … Read More

OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  … Read More

OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA Cafe, click here. The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More

VMM, VIP, OVM, Accellera, verification IP, UVM

Visit Booth 1383 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from 4:30 p.m. to 6:00 p.m. The Open Verification Methodology (OVM) is the industry’s open and  interoperable solution, guaranteed to run on … Read More

UVM, DAC, design automation conference, Accellera, ovmworld, flexray, OVM

UVM: Charting the New Territory At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion.  While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users.  UVM is at is simplest, just OVM.  If you know OVM; you know UVM. While OVM and … Read More

Accellera, DAC, 47DAC, UVM, OVM

Easier DUT to Testbench Connections This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench.  The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA. This extension also introduces the dual top methodology. This methodology isolates the connections between the … Read More

UVM, Verification Methodology, Accellera

The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available. While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM.  In April 2010, we made available at www.ovmworld.org an early version of UVM EA.  It has now been updated … Read More

Functional Verification, OVM, Accellera, VIP-TSC, UVM, UVM E.A.