Mentor Blogs

Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for … Read More

interoperability forum, Register Package, Accellera, UVM, VIP-TSC, synopsys

Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC).  Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate. As … Read More

OVM, ral, Accellera, UVM, VIP-TSC

Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently. Further, as part of the Accellera VIP-TSC UVM development … Read More

OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  … Read More

OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA Cafe, click here. The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More

VMM, VIP, OVM, Accellera, verification IP, UVM

Visit Booth 1383 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from 4:30 p.m. to 6:00 p.m. The Open Verification Methodology (OVM) is the industry’s open and  interoperable solution, guaranteed to run on … Read More

UVM, DAC, design automation conference, Accellera, ovmworld, flexray, OVM

UVM: Charting the New Territory At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion.  While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users.  UVM is at is simplest, just OVM.  If you know OVM; you know UVM. While OVM and … Read More

Accellera, DAC, 47DAC, UVM, OVM

Easier DUT to Testbench Connections This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench.  The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA. This extension also introduces the dual top methodology. This methodology isolates the connections between the … Read More

UVM, Verification Methodology, Accellera

The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available. While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM.  In April 2010, we made available at www.ovmworld.org an early version of UVM EA.  It has now been updated … Read More

Functional Verification, OVM, Accellera, VIP-TSC, UVM, UVM E.A.

Accellera and The SPIRIT Consortium Merger is Complete An open SystemVerilog requirements gathering meeting sponsored by the IEEE Design Automation Standards Committee’s (DASC) SystemVerilog Study Group was hosted at Mentor Graphics after DVCon 2010. While the meeting room was packed with many of the world’s SystemVerilog cognoscenti – as well as many from around the world on the phone. Dave Rich … Read More

IEEE 1800, Accellera, The SPIRIT Consortium, Spirit

Companion UVM-EA OVM Compatibility Overlay Kit for Available for Download Mentor Graphics has made available its UVM-EA starter kit to promote OVM users’ feedback on UVM. As I wrote in an earlier blog, Accellera has defined specific modifications to OVM 2.1.1 to create UVM-EA.  The Mentor Graphics version of the UVM-EA can be downloaded here.  The UVM-EA starter kits passes all our Questa 6.6 regression … Read More

UVM Early Adopter, Verification Methodology, Interoperability, OVM, Accellera, UVM, UVM E.A.

Requirements set for Accellera UVM-EA (Early Adopter) Release This was a productive week for Accellera. After months of discussions, the Accellera Verification IP Technical Subcommittee (VIP-TSC) voted to adopt OVM 2.1.1 as the base of its verification methodology. Accellera’s OVM version will be called UVM. In adopting OVM 2.1.1, Accellera signaled it will make further changes. The VIP-TSC has … Read More

Methodology, OVM, Accellera, UVM

… To Advance Technology for Humanity It is a humbling honor to have been elected chair of the IEEE Standards Association’s (SA) Corporate Advisory Group (CAG).  While Corporate Membership in the IEEE SA has been an element of the organization from its inception, it has only been in recent years that it has started to bring the voice of global industry into the IEEE’s standards making process.  As … Read More

VHDL, Accellera, 1076, CAG

3 – 2 – 1 – DOWNLOAD! As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness.  As of today, it is now ready for download and use.  With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera … Read More

OVM, Accellera, VIP-TSC, VMM