Posted Feb 5, 2010, by Thomas Bollaert
The latest edition of Chip Design Magazine features an insightful head-to-head discussion between Atrenta’s Kiran Vittal and Mentor’s Shawn McCloud. The topic: how to best achieve power-optimized RTL. Should low-power optimizations be performed in the RTL? Or is there more potential for power savings when starting from a more abstract design representation? The two industry experts share their viewpoints.
Atrenta’s … Read More
Tags:
Catapult,
Chip Design Magazine,
Atrenta,
High-Level Synthesis,
Low-Power
Posted Jan 23, 2010, by Thomas Bollaert
When adopting new methodologies, measuring and understanding the actual return on investment is always an important thing to do. While it is usually easy to see the upfront costs – the investment – it is equally easy to overlook the other half of the equation – the actual return.
In this video I’ll share with you the example of an ROI calculation which a Catapult customer did a little while ago.
… Read More
Tags:
ROI,
Video,
Catapult
Posted Aug 9, 2009, by Thomas Bollaert
A couple of weeks ago, I started explaining how sequential C++ could be parallelized to produce high-performance concurrent hardware. In the first two posts (part 1 and part2) I developed the notions of resource bottlenecks and spatial parallelism; in this third post we will explain the notion temporal parallelism. This concept is essential as it allows parallelizing data dependant operations - a case … Read More
Tags:
High-Level Synthesis,
Catapult,
C Synthesis,
Sequential,
Parallelism
Posted Aug 1, 2009, by Dan Gardner
For those of you ASIC and FPGA hardware designers who have been dismissing C++ as a hardware description language (HDL), this blog is for you. I’ve been thinking back to some of my first hardware design projects to prove to myself that it is really much easier to learn C++ for hardware design than it was to figure out VHDL or Verilog for the first time.
Maybe, it is all the gray hair showing my decade … Read More
Tags:
High-Level Synthesis,
HLS,
ESL,
Catapult
Posted Jul 30, 2009, by Thomas Bollaert
A couple of hours after Hitachi Telecom’s inspiring presentation on a 2 million gate enhanced Forward-Error Correcting (FEC) system design with Catapult C, Nitin Chawla of STMicroelectronics gave extensive details on his experience with C synthesis for complex signal processing applications.
Differentiating the high-level synthesis input languages
Chawla opened his talk by comparing the … Read More
Tags:
Frequency Domain Processor,
High-Level Synthesis,
Catapult,
C Synthesis,
User Testimonial,
FFT,
DAC,
STMicroelectronics
Posted Jul 30, 2009, by Thomas Bollaert
Looking at my San Francisco schedule, Tuesday was clearly the day I was most looking forward to. Besides the usual panels and meetings, I was really eager to hear the two testimonials from Hitachi Telecom and STMicroelectronics on their experiences with C Synthesis. Both Natori-san and Nitin Chawla provided personal and insightful views on their adoption of HLS
82% time reduction with C synthesis
Hitachi … Read More
Tags:
High-Level Synthesis,
Catapult,
C Synthesis,
User Testimonial,
FEC,
DAC,
Hitachi
Posted Jul 28, 2009, by Thomas Bollaert
It is early Sunday morning in San Francisco. I am tranquilly having breakfast in a nice little coffee place when a cheerful crowd draped in silvery blankets enters the bar. It takes me a few minutes to figure out that I am facing a group of people who just finished the San Francisco Marathon!
I have to admire the determination it takes to prepare, run and complete such a race. Meanwhile, the Moscone … Read More
Tags:
High-Level Synthesis,
Low-Power,
C Synthesis,
Multi-Block Synthesis,
Vista,
Catapult,
DAC
Posted Jul 22, 2009, by Thomas Bollaert
Whether for creating greener electronic products, complying with environmental regulations or extending a battery-powered device’s operating time; low-power design is becoming a necessity for most new applications.
Mentor Graphics recently announced significant advances for low-power design through its Catapult C high-level synthesis tool. During the synthesis process, a tool like Catapult C will … Read More
Tags:
Sequence,
Partners,
High-Level Synthesis,
Low-Power,
C Synthesis,
Atrenta,
Catapult,
DAC
Posted Jun 29, 2009, by Thomas Bollaert
The many man years of effort we have invested in the newly announced Catapult technology can hardly be summarized in a simple press release. We expect that the true novelty of the Catapult approach for synthesizing and verifying the combination of control-logic and algorithmic blocks from pure C++ will stimulate your curiosity and interest.
We’ve done our best to anticipate your questions. We’ve set … Read More
Tags:
Control-Logic Synthesis,
HLS,
C Synthesis,
Twitter,
Low-Power,
Catapult
Colin Walls
John Wilson
John Parry
Robin Bornoff
John Isaac
Paul Johnston
Simon Favre
Nazita Saye
John Ferguson
Arvind Narayanan
Boris Marovic
Jim Martens
David Wiens
Ralph Zak
David Tatchell
Dave Rich
John Day
Steve McKinney
Mark Forbes
Tom Fitzpatrick
Dennis Brophy
Michael Stamper
Michael White
Mike Jensen
Steve Collis