Posted Jun 6, 2011, by Thomas Bollaert
One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL.
Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new … Read More
Tags:
Vista,
DAC,
esl,
Catapult C,
TSMC,
Verification,
High-Level Synthesis,
How-to
Posted Apr 5, 2011, by Thomas Bollaert
“In recent times, ESL design methodologies have been the talk of the semiconductor design community and have found increasing acceptance. Most of the recent publications have given information on design flow needs and an high level overview of the (C/C++/SystemC) based high level synthesis design process using a small block level design scenario. Although productivity benefits for ESL methodologies … Read More
Tags:
RTL,
OFDM,
STMicroelectronics,
C synthesis,
Catapult C,
ANSI C++,
User Testimonial,
FFT,
Full-Chip,
High-Level Synthesis,
Control-Logic Synthesis,
DesignCon
Posted Apr 1, 2011, by Thomas Bollaert
You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the … Read More
Tags:
SystemC,
Full-Chip,
User Testimonial,
Catapult C,
control,
C++,
High-Level Synthesis,
Deepchip,
ESNUG,
Control-Logic Synthesis,
Cooley
Jim Martens
John Day
J VanDomelen
Nazita Saye
Michael Ford
Robin Bornoff
Dennis Brophy
Mike Jensen
Colin Walls
Tom Fitzpatrick
Max Clark
Patrick Carrier
Mark Laing
Travis Mikjaniec
Chris Hallinan
Christopher Hallinan
Bernard Sutton