Posted Apr 5, 2011, by Thomas Bollaert
“In recent times, ESL design methodologies have been the talk of the semiconductor design community and have found increasing acceptance. Most of the recent publications have given information on design flow needs and an high level overview of the (C/C++/SystemC) based high level synthesis design process using a small block level design scenario. Although productivity benefits for ESL methodologies … Read More
Tags:
RTL,
OFDM,
STMicroelectronics,
C synthesis,
Catapult C,
ANSI C++,
User Testimonial,
FFT,
Full-Chip,
High-Level Synthesis,
Control-Logic Synthesis,
DesignCon
Posted Apr 1, 2011, by Thomas Bollaert
You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the … Read More
Tags:
SystemC,
Full-Chip,
User Testimonial,
Catapult C,
control,
C++,
High-Level Synthesis,
Deepchip,
ESNUG,
Control-Logic Synthesis,
Cooley
Posted Dec 2, 2009, by Thomas Bollaert
In a very thorough article published yesterday, Electronic Design’s David Maliniak takes a close look at ESL tools and how they are taking center stage as designers move up the abstraction ladder. The article reviews the details of the two major additions in the latest release of Catapult C: low-power optimizations and control-logic synthesis.
“Launched in 2004, Mentor Graphics’ Catapult C has seen … Read More
Tags:
Low Power,
Control-Logic Synthesis
Posted Jun 29, 2009, by Thomas Bollaert
The many man years of effort we have invested in the newly announced Catapult technology can hardly be summarized in a simple press release. We expect that the true novelty of the Catapult approach for synthesizing and verifying the combination of control-logic and algorithmic blocks from pure C++ will stimulate your curiosity and interest.
We’ve done our best to anticipate your questions. We’ve set … Read More
Tags:
High-Level Synthesis,
Control-Logic Synthesis
Posted Jun 29, 2009, by Thomas Bollaert
On June 29, Mentor Graphics’ Catapult C Synthesis team unveiled breakthrough enhancements leading the way to full-chip synthesis. After pioneering C synthesis in 2004 and hierarchical synthesis in 2006, Catapult C now introduces groundbreaking technology around control-logic synthesis and low-power optimizations.
The control-logic synthesis extensions significantly widen the application scope of high-level … Read More
Tags:
Control-Logic Synthesis,
High-Level Synthesis,
Catapult C Synthesis,
Low Power
Posted Jun 29, 2009, by Thomas Bollaert
The design world is commonly separated in two camps: algorithmic-oriented designs and control-dominated designs. By becoming the first High-Level Synthesis tool to synthesize Control-Logic from pure C/C++, Catapult C makes the promise that these two camps can be united enabling full systems to be modeled, verified and synthesized all together.
But this cleanly divided view of the world is only a convenient … Read More
Tags:
Control-Logic Synthesis,
High-Level Synthesis,
Catapult C Synthesis
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