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Posts tagged with 'FinFET'

13 May, 2014

Shelly Stalnaker With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased … Read More

P&R, Olympus-SoC, place and route, 16nm, 20nm, 10nm, IC Design, Multi-Patterning, double patterning, FinFET

16 Jan, 2014

Shelly Stalnaker With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More

test pattern, Tessent, defect detection, ATPG, IC, scan test, fault models, FinFET

16 Jan, 2014
IC Design

FinFET Fever...or FinFET Fear?

Posted by Shelly Stalnaker

Shelly Stalnaker All the major foundries have announced FinFET technologies. FinFETs hold the promise of lower power usage and better area utilization, as well as traditional scaling improvements. Aaaaand…the thought of implementing them may be scaring the willies out of a lot of designers. How do I design these things? How do I know what the design needs? How do I verify them? Well, first, take a deep breath. … Read More

Parasitic Extraction, Foundry, transistor, 16nm, 22nm, 14nm, FinFET, Calibre, circuit design

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

13 Dec, 2013

Shelly Stalnaker While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. In this white paper from David Abercrombie, learn what multi-patterning is, why you need it, and how Calibre Multi-Patterning software … Read More

odd cycle, multipatterning, 16nm, Lithography, 20nm, mandrel, Mentor Graphics, Multi-Patterning, 14nm, colorless design, layout decomposition, D2S, LELE, anchor path, litho, Calibre Multi-Patterning, litho-etch-litho-etch, FinFET, double patterning, Foundry, warning rings, Parasitic Extraction, spacer-assisted, triple patterning, spacer is dielectric, spacer is mask, SID SADP, SIM SADP, pin coloring, pitch-split

7 Dec, 2012
IC Design

Battle of Fins and BOXes

Posted by Arvind Narayanan

Arvind Narayanan Do FDSOI and FinFET provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI?  Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits … Read More

FD-SOI, fin grid, dual gate, MugFET, Tri-gate, FinFET, full depleted SOI

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