Mentor Blogs

Posts tagged with 'Formal Verification'

23 Apr, 2013

Harry Foster This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

26 Jun, 2011

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 8 click here), I focused on some of the 2010 Wilson Research Group findings related to design and verification language trends. … Read More

Emulation, testbench, Functional Verification, Formal Verification

4 Apr, 2011

Harry Foster   Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues this discussion. I stated in my previous … Read More

Functional Verification, Verification, Formal Verification

26 Jul, 2010

Ping Yeung For years one of the objectives in EDA has been to make formal property checking easy to use and its results easy to understand. With the Automatic formal check feature in the June release of the 0-In Formal tool version 3.0, I think we have made significant progress in this area. The feature, which predefines a set of assertion rules to look for design issues automatically, makes formal technology … Read More

automatic formal check, formal property checking, Assertion-Based Verification, SVA, Formal Verification, functional coverage

25 Jul, 2010

Harry Foster What does the word performance mean to you? Speed? Well, obviously speed is an important characteristic. Yet, if the team is running in the wrong direction, it really doesn’t matter how fast they are going. How about accomplishment? After all, we do assess an employee’s or project team’s accomplishments using a process we refer to as a performance review. What about efficiency, which is a ratio comparing … Read More

Formal Verification, Functional Verification, Add new tag