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Posts tagged with 'Foundry'

10 Jun, 2014
IC Design

Goooaaaaaaaaaaaaal!

Posted by Shelly Stalnaker

Shelly Stalnaker The World Cup is here! Every four years, the culmination of hundreds of qualifying matches around the world brings the best national teams together for nearly a month of intense competition to determine the world champion football team (Sorry, USA, but it’s football everywhere else). New national uniforms are unveiled, shoe companies vie to sponsor the best players and teams with their most advanced … Read More

IC Verification, ic manufacturing, Mentor Graphics, DRC, DRM, Design Rules, Foundry, process flow, IC Design, Fabless

21 Mar, 2014
IC Manufacturing

I See the Light!

Posted by Shelly Stalnaker

Shelly Stalnaker Photonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design. The biggest challenge in applying CMOS foundry processes to silicon photonics is creating … Read More

Foundry, IC Design, silicon photonics, waveguides, ic manufacturing, Michael White

19 Mar, 2014
IC Design

Déjà Vu All Over Again

Posted by Shelly Stalnaker

Shelly Stalnaker Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm … Read More

Foundry, IC Design, 14nm, 16nm, 10nm, advanced node, leading-edge, Semiconductor, Christen Decoin, 20nm, technology node, 28nm

21 Jan, 2014

Shelly Stalnaker Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). Until recently, companies could reduce TAT by adding computer hardware, fine-tuning OPC recipes, improving input hierarchical handling of designs, and upgrading to new software versions with new functionality and performance … Read More

cluster management, Fabless, Calibre CalCM, resource management, turnaround time, Foundry, ic manufacturing

16 Jan, 2014
IC Design

FinFET Fever...or FinFET Fear?

Posted by Shelly Stalnaker

Shelly Stalnaker All the major foundries have announced FinFET technologies. FinFETs hold the promise of lower power usage and better area utilization, as well as traditional scaling improvements. Aaaaand…the thought of implementing them may be scaring the willies out of a lot of designers. How do I design these things? How do I know what the design needs? How do I verify them? Well, first, take a deep breath. … Read More

Parasitic Extraction, Foundry, transistor, 16nm, 22nm, 14nm, FinFET, Calibre, circuit design

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

14 Jan, 2014

Shelly Stalnaker Do you have a product that has been manufactured for quite some time at a high volume? If so, maybe it makes financial sense to chase down that last 1% of yield loss. In Geir Eide’s article on EDN.com, he explains how diagnosis-driven yield analysis (DDYA) can help you quickly and efficiently identify the root cause of yield loss, and separate design-based from process-based yield loss. Still … Read More

yield loss, diagnosis-drive yield analysis, Foundry, DDYA, root cause analysis, root cause deconvolution, layout-aware can diagnosis, RCD

13 Dec, 2013
IC Design

Qualification Is Just the Beginning

Posted by Shelly Stalnaker

Shelly Stalnaker Press releases can make it seem like EDA tool qualification for a particular IC process node is the “end game.” But in truth, qualification is just the first publicly visible step of ongoing collaborations between an EDA vendor and the foundry. Michael White takes you behind the curtain for a peek at what goes on during qualification from start to finish, as part of his ongoing Silicon Edge series … Read More

tool qualification, tapeout, DRM, Foundry, design rule manual, process design kit, rule deck, IC, PDK

13 Dec, 2013

Shelly Stalnaker Just like blueprints give an architect a visual representation of a building, design patterns provide engineers with a visual depiction of complex layout geometries. Design patterns have become a useful tool throughout design, verification, and test processes. This Design-to-Silicon white paper explains how Calibre Pattern Matching software can help you implement automated pattern capture and pattern … Read More

pattern capture, Mentor Graphics, Pattern Matching, D2S, Design Rule Checking, Calibre Pattern Matching, SVRF, Foundry, hotspot detection, yield detractors, design waivers, DRC

13 Dec, 2013

Shelly Stalnaker While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. In this white paper from David Abercrombie, learn what multi-patterning is, why you need it, and how Calibre Multi-Patterning software … Read More

odd cycle, multipatterning, 16nm, Lithography, 20nm, mandrel, Mentor Graphics, Multi-Patterning, 14nm, colorless design, layout decomposition, D2S, LELE, anchor path, litho, Calibre Multi-Patterning, litho-etch-litho-etch, FinFET, double patterning, Foundry, warning rings, Parasitic Extraction, spacer-assisted, triple patterning, spacer is dielectric, spacer is mask, SID SADP, SIM SADP, pin coloring, pitch-split

13 Dec, 2013
IC Design

The Trouble With Triples—Part 1

Posted by Shelly Stalnaker

Shelly Stalnaker Triple patterning is not just double patterning with an extra color! Our resident expert, David Abercrombie, introduces the basics of triple patterning and explains the new challenges it brings to the layout and verification flow in his ongoing series for for SemiconductorEngineering’s Manufacturing and Design segment. If you’re even thinking about advanced node designs, this is a must-read. Bonus references … Read More

Foundry, DRC, multipatterning, 14nm, 16nm, 10nm, triple patterning, double patterning, 20nm, decomposition

13 Dec, 2013

Shelly Stalnaker Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More

DRC, digital IC, Foundry, tech files, tapeout, 14nm, rule decks, signoff, 16nm, SoC, 10nm, SVRF, IP, Design Rule Checking, P&R, router, 20nm, Routing, Debugging

13 Dec, 2013

Shelly Stalnaker No one wants to edit a foundry rule deck—it’s like tugging on Superman’s cape. But there are many ways to customize the input to a Calibre job without modifying the foundry rule deck. To learn more, watch one of our short, to-the-point How-To videos on our IC Nanometer Design channel on YouTube. Oh, and if you can’t find what you’re looking for? Suggest a new topic! … Read More

runsets, rule decks, configurations, DRC, Calibre, rule checks, ERC, Foundry

5 Apr, 2013

Gene Forte Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More … Read More

SRAF, RET, 20nm, 22 nm, 14nm, manufacturability, OPC, Foundry, Lithography

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