Emulation 104 -- Running More Tests in Less Time
In an earlier blog I talked about the value of emulation in terms of providing direct project cost and schedule reductions that generally dwarf the actual costs of emulation systems. I have been asked by some to provide a “prequel” discussion, with a higher level description of the SoC verification problem and how emulation systems address verification challenges.
Rather than trying to cover the … Read More
Tags: SoC Verification, Emulation, FPGA Boards, ASIC Emulation, SoC Emulation, SoC Simulation, FPGA Systems, Simulation Acceleration
Jim Martens
Harry Foster
John Day
J VanDomelen
Paul Johnston
Robin Bornoff
Dennis Brophy
Mike Jensen
Colin Walls
Jay Gorajia
Mark Olen
Travis Mikjaniec
Per Viklund