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Posts tagged with 'Full-Chip'

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A Designer’s Perspective on ESL Methodologies for an OFDM Modem Design

Posted Apr 5, 2011, by Thomas Bollaert

“In recent times, ESL design methodologies have been the talk of the semiconductor design community and have found increasing acceptance. Most of the recent publications have given information on design flow needs and an high level overview of the (C/C++/SystemC) based high level synthesis design process using a small block level design scenario. Although productivity benefits for ESL methodologies … Read More

Tags: RTL, OFDM, STMicroelectronics, C synthesis, Catapult C, ANSI C++, User Testimonial, FFT, Full-Chip, High-Level Synthesis, Control-Logic Synthesis, DesignCon

ESL

Catapult C and the 7 Samuraïs

Posted Apr 1, 2011, by Thomas Bollaert

You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the … Read More

Tags: SystemC, Full-Chip, User Testimonial, Catapult C, control, C++, High-Level Synthesis, Deepchip, ESNUG, Control-Logic Synthesis, Cooley

Electromagnetic (EM) Design & Simulation Software

Via modeling - what do I really need?
Patrick Carrier (Posted 11/2/11)
How can we obtain the s-parameters data with non-50 normalization?
Jian Zheng (Posted 2/28/11)
The effects of different bends on performances of wideband digital circuits.
Jian Zheng (Posted 8/26/10)
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Embedded Software

GTC - mission accomplished
Colin Walls (Posted 5/21/12)
Measuring RTOS performance - a Web seminar
Colin Walls (Posted 5/14/12)
The value of MISRA-compliant software
John Day (Posted 5/8/12)
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ESL

Mentor ESL in TSMC Reference Flow 12
Thomas Bollaert (Posted 6/6/11)
48th DAC - Gary’s Magic Formula
Thomas Bollaert (Posted 6/6/11)
DAC: 9th ESL Symposium
Thomas Bollaert (Posted 5/16/11)
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Valor MSS PCB Manufacturing Systems Solutions

The World Is Trying It’s Hardest To Leave Me Unimpressed….
Michael Ford (Posted 5/17/12)
The value of consolidated data preparation
Mark Laing (Posted 5/15/12)
Get the little things right - consistently
Bernard Sutton (Posted 5/15/12)
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Electrical & Wire Harness Design

Tracking telematics in China
John Day (Posted 5/14/12)
Comfy cars
John Day (Posted 4/30/12)
Packages and Passengers
J VanDomelen (Posted 4/28/12)
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Functional Verification

Dave Rich Featured on EEWeb
Tom Fitzpatrick (Posted 5/12/12)
How Did I Get Here?
Dennis Brophy (Posted 3/22/12)
Expanding the Verification Academy!
Harry Foster (Posted 2/26/12)
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IC Manufacturing

Our OWL ran down the batteries after only 1 month !
Steve Collis (Posted 1/29/10)
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IC Design

TSMC 28nm yield (SemiWiki)
Simon Favre (Posted 3/5/12)
DAC 2011 is upon us!
Simon Favre (Posted 5/11/11)
Mentor Graphics User to User (U2U)
John Ferguson (Posted 4/11/11)
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Mechanical Analysis

Impossible Made Possible
Nazita Saye (Posted 5/21/12)
Hockey Puck Aerodynamics
Travis Mikjaniec (Posted 5/18/12)
Top 10 Things I Learned From Engineers
Nazita Saye (Posted 5/15/12)
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PCB Design Software & Tools

PADS Tips and Tricks: Pin Swapping
Jim Martens (Posted 5/15/12)
Turn off your phone!
Patrick Carrier (Posted 5/3/12)
Is it SSN or is it Crosstalk?
Patrick Carrier (Posted 5/2/12)
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System Modeling

Rooster Tail Engineering
Mike Jensen (Posted 5/3/12)
Automotive IESF 2012
Mike Jensen (Posted 4/25/12)
Teaching and Learning CAN Bus
Mike Jensen (Posted 4/10/12)
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Vehicle System Design

IESF 2011 Moves to Frankfurt
Mike Jensen (Posted 9/26/11)
Making automotive electronics reliable
John Day (Posted 9/29/10)
Visteon’s concept car debuts in Paris
John Day (Posted 9/27/10)
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Aerospace and Military Solutions

Packages and Passengers
J VanDomelen (Posted 4/28/12)
Boeing tenacity finds its bounty
J VanDomelen (Posted 4/27/12)
Birth of a giant, and a giant rivalry
J VanDomelen (Posted 4/26/12)

Automotive Solutions

Tracking telematics in China
John Day (Posted 5/14/12)
Comfy cars
John Day (Posted 4/30/12)
Where would you like to charge your EV?
John Day (Posted 4/27/12)

Low Power Solutions

See ya at the Finish Dad!
Steve Collis (Posted 3/27/10)
Time to Power Diet!
Steve Collis (Posted 2/26/10)
The rest of my family need mobile devices that can charge themselves!
Steve Collis (Posted 2/12/10)

Manufacturing Variability Solutions

How do you define DFM?
David Abercrombie (Posted 5/19/09)
Are Design Rules Broken?
David Abercrombie (Posted 5/15/09)

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Roger said I do have to agree. Learning to be computer engien... in X-Ray Vision Glasses … Here and Now
Mutlu said Hi John,Thanks for the comment.I think you and I a... in UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
Dave Rich said Make sure you are using the 32-bit version of Ques... in Using the UVM 1.0 Release with Questa
BK said How to resolve error in simulating UVM1.1 W7(64-bi... in Using the UVM 1.0 Release with Questa
(Wasted) Effort Spent In Verification | AgileSoC said [...] in that series comes via my new favorite har... in Part 5: The 2010 Wilson Research Group Functional Verification Study
(Wasted) Effort Spent In Verification | AgileSoC said [...] just spent a few minutes reading Harry Foste... in Prologue: The 2010 Wilson Research Group Functional Verification Study
More Than Two Decades and Still Going Strong; FloTHERM and FloVENT V9.3 Now Released « Robin Bornoff's blog said [...] XML strategy, whereby geometry data can be a... in FloTHERM and its new XML neutral file format
omer said Hello Dave, Thank you very much for progressive e... in SystemVerilog Coding Guidelines: Package import versus `include
Michael Ford said The currently most popular aspect of design for re... in Extreme Design!

Mentor Blogs

Posts tagged with 'Full-Chip'

A Designer’s Perspective on ESL Methodologies for an OFDM Modem Design

Catapult C and the 7 Samuraïs

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