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Mentor Blogs

Posts tagged with 'Functional Verification'

4 Feb, 2014

Joe Rodriguez Marketing teams at FPGA vendors have been busy as the silicon nanometer geometry race escalates. Altera is “delivering the unimaginable” while Xilinx is offering “all programmable SoCs” to design centers. It’s clear that the SoC has become more accessible to a broader market today and that FPGA vendors have staked out a solid technology roadmap for the near future. Do marketing … Read More

Verilog, Verification, VHDL, Code Coverage, Coverage, Assertions, FPGA, Functional Verification

30 Oct, 2013

Mark Olen MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from Tuesday October 29 through Thursday October 31st, but don’t worry, there’s nothing to be scared about.  The theme is “Where Intelligence Counts”, and in fact as a platinum sponsor of the event, Mentor Graphics is excited to present no less than ten technical and training sessions about … Read More

testbench, SoC, Verification, Formal Verification, functional coverage, ARM, Verification Academy, iTBA, Functional Verification, Intelligent Testbench Automation

26 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

19 Aug, 2013

Harry Foster Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (Part 9 click here), I focused on some of the 2012 Wilson Research Group findings related to design and verification language and library … Read More

testbench, UVM, Assertion-Based Verification, Coverage, Accellera, Verification Academy, functional coverage, Functional Verification

12 Aug, 2013

Harry Foster Language and Library Trends (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 8 click here), I focused on design and verification language trends, as identified by the Wilson Research Group study. This blog presents additional … Read More

SVA, UVM, Accellera, Assertion-Based Verification, Verification Methodology, OVL, PSL, Functional Verification

5 Aug, 2013

Harry Foster Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 7 click here), I focused on some of the 2012 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present … Read More

IEEE 1800, RTL, VHDL, 1364, testbench, Verification, Verification Academy, 1076, Verilog, Functional Verification, SystemC, Accellera, functional coverage

29 Jul, 2013

Harry Foster Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. In this blog, I focus on some of the 2012 Wilson Research Group … Read More

testbench, UVM, Accellera, Formal Verification, Verification, IEEE 1800, Functional Verification

22 Jul, 2013

Harry Foster Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues that discussion. I stated in my previous blog that … Read More

Verification Academy, Verification, Verification Methodology, Formal Verification, Functional Verification, Accellera, UVM, IEEE 1800

15 Jul, 2013

Harry Foster   Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of the amount of effort spent in verification. Directly asking study participants … Read More

Functional Verification, Accellera, Verification Academy, Verification Methodology, Verification

8 Jul, 2013

Harry Foster Reuse Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on clocking and power management.  In this blog, I focus on design and verification reuse trends. As I mentioned in my prologue blog to this series (click here), one interesting trend that … Read More

Functional Verification, Reuse, Formal Verification, Verification Academy, Verification Methodology

28 Jun, 2013

Harry Foster Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends. Independent Asynchronous Clock Domains Figure 1 shows the percentage … Read More

Verification Academy, Verification, Verification Methodology, Functional Verification, Accellera, Wilson Research Group Study, UPF, IEEE 1801, Low Power

8 May, 2013

Harry Foster  Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.  This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing … Read More

Functional Verification, Accellera, Verification Academy, IEEE 1800, Verification

3 May, 2013

Dave Rich A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog … Read More

Verification, Functional Verification, Verilog

23 Apr, 2013

Harry Foster This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

25 Feb, 2013

Dave Rich Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program. As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements … Read More

Functional Verification, Accellera

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