Effort Spent On Verification
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of amount of effort spent in verification.
I have been on the technical program … Read More
Reuse Trends
This blog is a continuation of a series of blogs, which presents the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I focus on design and verification reuse trends.
Design Composition Trends
Figure 1 shows the mean design composition trends, which compares the 2007 Far West Research study (in blue) with the 2010 Wilson Research … Read More
Design Trends (Continued)
In Part 1 of this series of blogs, I focused on design trends (click here) as identified by the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on embedded processor, power management, and clock domain trends.
Embedded Processors
In Figure 1, we see the percentage … Read More
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the electronic industry’s state and trends in design and verification at that point in time. However, after the 2004 study, no other industry studies were conducted, which left a void in indentifying industry trends.
To address this void, … Read More
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James.
The goal of verification planning … Read More
Tags: Functional Verification, OVM, Assertion-Based Verification, Verification Methodology, UVM, Verification Academy
What does the word performance mean to you?
Speed? Well, obviously speed is an important characteristic. Yet, if the team is running in the wrong direction, it really doesn’t matter how fast they are going.
How about accomplishment? After all, we do assess an employee’s or project team’s accomplishments using a process we refer to as a performance review.
What about efficiency, which is a ratio comparing … Read More
Tags: Formal Verification, Functional Verification, Add new tag
The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available.
While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM. In April 2010, we made available at www.ovmworld.org an early version of UVM EA. It has now been updated … Read More
Tags: Functional Verification, OVM, Accellera, VIP-TSC, UVM, UVM E.A.
In my last blog I stated I was an evangelist for using emulation to verify SoC designs. I defined Emulation Systems as verification systems which provide (1) Vector and transaction-based simulation acceleration and (2) in-circuit emulation (ICE) capability to perform system integration and test using real world data before silicon is available. Emulation systems are typically built on custom emulation … Read More
Tags: Emulation, Functional Verification, FPGA Prototyping, System Verilog, VMM, OVM, SoC Verification
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