Posted Jun 6, 2011, by Thomas Bollaert
One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL.
Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new … Read More
Tags:
Vista,
DAC,
esl,
Catapult C,
TSMC,
Verification,
High-Level Synthesis,
How-to
Posted Jun 6, 2011, by Thomas Bollaert
Last night, in his traditional DAC-opening presentation, Gary Smith addressed the crowd with a loud and clear message about the cost of doing hardware design. Design costs are steadily increasing and this is draining life and blood out of the industry. When chip design costs reach $25M, VCs stop funding start-ups. When costs reach $50M, continued Gary Smith, even IDMs struggle to afford ASIC developments.
So … Read More
Tags:
cost,
DAC,
ASIC,
High-Level Synthesis,
How-to,
esl,
Gary Smith
Posted May 16, 2011, by Thomas Bollaert
If you are going to DAC this year, then you must attend the 9th Annual ESL Symposium and not just because there is free lunch or you need the new Apple iPad 2. This year, Wally Rhines will moderate a very impressive panel line-up:
Gadi Singer - Intel
Vice President, Intel Architecture Group
General Manager, System-on-Chip Enabling Group
John Goodenough - ARM
Vice President of Design Technology and … Read More
Tags:
User Testimonial,
Freescale,
STMicroelectronics,
High-Level Synthesis,
esl,
DAC,
intel,
ARM
Posted Apr 25, 2011, by Thomas Bollaert
In my last two posts, I introduced the question that proved the most challenging in the HLS Bluebook quiz (here) and presented some fundamental concepts about loop unrolling and loop pipelining and explained why answer 2 was not the right one (here).
Let’s now see what happens in the case of answer 1, when we unroll LOOP0 by 4 and pipeline the design with II=1.
Partially unrolling by 4 means … Read More
Tags:
High-Level Synthesis,
Unrolling,
Bluebook,
C synthesis,
HLS,
ANSI C++,
Loop,
Pipelining,
How-to,
Learning
Posted Apr 19, 2011, by Thomas Bollaert
The dust has settled and four winners have emerged from the HLS Bluebook contest, and this week, as promised, I will discuss the question that proved to be the most challenging in third and final round of the contest.
The culprit was the following question, which only 15% of the contenders answered correctly:
HLS Contest - Round 3, Question 1
What this simple C code does is: reading 8 input values … Read More
Tags:
High-Level Synthesis,
Bluebook,
Unrolling
Posted Apr 5, 2011, by Thomas Bollaert
“In recent times, ESL design methodologies have been the talk of the semiconductor design community and have found increasing acceptance. Most of the recent publications have given information on design flow needs and an high level overview of the (C/C++/SystemC) based high level synthesis design process using a small block level design scenario. Although productivity benefits for ESL methodologies … Read More
Tags:
RTL,
OFDM,
STMicroelectronics,
C synthesis,
Catapult C,
ANSI C++,
User Testimonial,
FFT,
Full-Chip,
High-Level Synthesis,
Control-Logic Synthesis,
DesignCon
Posted Apr 1, 2011, by Thomas Bollaert
You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the … Read More
Tags:
SystemC,
Full-Chip,
User Testimonial,
Catapult C,
control,
C++,
High-Level Synthesis,
Deepchip,
ESNUG,
Control-Logic Synthesis,
Cooley
Posted Mar 7, 2011, by Thomas Bollaert
Good news for the industry: the DATE (Design, Automation, and Test in Europe) conference is back to growth. And perhaps it is not a surprise given that this year the event is being held in Grenoble. With its great views on the snowy Alps, Grenoble is emerging has the major hub of the electronic and semiconductor industry in Europe.
3D ICs, Low-power, ESL… The rich conference program covers all hot … Read More
Tags:
C synthesis,
High-Level Synthesis,
Bluebook,
User Testimonial,
STMicroelectronics,
Tutorial
Posted Feb 18, 2011, by Thomas Bollaert
Oh my, what a busy ESL agenda! There is content for everyone, everywhere. Here is a list of no less than 7 compelling events. Virtual Prototyping, ESL Verification, High-Level Synthesis: make your choice. What’s on your agenda? Which events will you be attending?
SystemC Day 2011 - February 28th, San Jose, CA
High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application - … Read More
Tags:
User Testimonial,
EDA Tech Forum,
High-Level Synthesis
Posted Jan 21, 2011, by Thomas Bollaert
In a recently published white paper, authors Bruno Thery, Serge Mazer, Adrian Beames and Yvan Desmartin of STMicroelectronics describe their seven steps approach to achieve higher productivity using High-Level Synthesis (HLS) and how this was key to help them deliver working silicon in time for the Las Vegas CES in January 2010.
The white paper provides a detailed, step by step, description of how … Read More
Tags:
User Testimonial,
High-Level Synthesis
Jim Martens
John Day
J VanDomelen
Nazita Saye
Michael Ford
Robin Bornoff
Mike Jensen
Colin Walls
Tom Fitzpatrick
Patrick Carrier
Mark Laing
Travis Mikjaniec
Christopher Hallinan
Bernard Sutton