Posted Jan 13, 2011, by Patrick Carrier
You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation. IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface. These models are an addendum to the existing IBIS spec that contain executable models.
Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model. The executable … Read More
Tags:
SPICE,
Fasteye,
HyperLynx,
SERDES,
IBIS,
IBIS-AMI
Posted Apr 23, 2010, by Steve McKinney
To begin this series on fundamentals of signal integrity, lets start at the very beginning. Before you start doing any type of simulation or analysis, what do you have to do first, what information do you have to know? Your design probably has thousands of nets, are you going to simulate all of them?? Probably not, there’s not enough time for that and truthfully, it’s not really necessary. The first … Read More
Tags:
Modeling,
IBIS,
SI,
Critical Nets,
Edge Rate,
Signal Integrity,
high frequency nets,
HyperLynx,
EMI,
Fundamentals
Posted Jan 14, 2010, by Steve McKinney
If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface. AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers. Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More
Tags:
Multi-Gigabit,
Models,
SERDES,
ATM,
Xilinx,
Eye Diagram,
AMI,
IBIS 5.0,
SPICE,
V5,
Modeling,
HyperLynx,
Virtex 5,
Webinar,
IBIS
Posted Jan 6, 2010, by Mark Forbes
DesignCon is coming up in less than a month, February 1-4 in Santa Clara, CA (find your way to San Jose and turn left). This is a great show, and we at Mentor have put together some great sessions for you; and we have more than just technical content, we have some fun plans as well.
One of those fun things is a panel called “Science Fiction: Is It Really Fiction” Tuesday, February 2nd from 3:45 … Read More
Tags:
High Speed,
IBIS,
DesignCon,
SPICE,
SERDES,
SiP
Posted Oct 12, 2009, by Robin Bornoff
Lumped block package representation makes the best use of limited available data to simulate for an ‘indication’ of case temperature. Some indication is better than none but I wouldn’t bet on it, really, I wouldn’t. Accurate case and junction temperature prediction can only be realised with either a fully 3D detailed representation or an abstracted CTM (compact thermal model) representation. Here we’ll … Read More
Tags:
Thermal Resistor,
CTM,
Electronics Cooling,
Component,
SPICE,
Thermal Resistance,
IBIS