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Posts tagged with 'IC Design'

20 Aug, 2009

David Abercrombie I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

4 Aug, 2009
IC Design

David's DAC09 - White Paper Session

Posted by David Abercrombie

David Abercrombie I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

31 Jul, 2009
IC Design

David's DAC09 - Another Special Guest

Posted by David Abercrombie

David Abercrombie Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More

Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules

28 Jul, 2009
IC Design

David's DAC09 - Off to a great start!

Posted by David Abercrombie

David Abercrombie Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More

IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

2 Jul, 2009
IC Design

To Waive Or Not To Waive?

Posted by David Abercrombie

David Abercrombie That is the question! If you read my colleague John’s most recent posting “Waive of the future?”, you will understand the question. I was equally shocked as John to find that almost no one tapes out DRC clean anymore. I would add one other reason to John’s list as to why this has happened. I think the traditional DRC rules are broken. Please read my first post “Are Design Rules Broken?” for my stance … Read More

IC Verification, IC Design, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

30 Jun, 2009
IC Design

"Waive" of the Future?

Posted by John Ferguson

John Ferguson Many, many years ago, when I started in this business, I encountered something that I thought was surprising.  In my very first DRC benchmark, I was struggling with a particular rule.  The customer had given me a 0.25 micron layout, which they had successfully taped out.  My job was to write a rule file in the new tool to measure performance improvement.  My code matched the design rule manual and passed … Read More

IC Design, DRC

19 Jun, 2009

David Abercrombie One of the fundamental questions everyone asks about DFM is “why should I do it?” On the one hand this always strikes me as a funny question. I always look at DFM in the same way I think of automobile safety. Statistically, most people never get in a serious accident. So why would you spend so much money on airbags, antilock brakes, better seat belts, side door reinforcements, traction control, etc. … Read More

Yield, Design Quality, Design for Manufacturing, IC Verification, Reliability, Physical Verification, IC Design

17 Jun, 2009

Karen Chow More and more digital processing functions isolated into multiple power domains, hundreds or thousands of analog-digital interconnections, operating frequencies always closer to pure RF — clearly, genuine full-chip verification of complex mixed-signal systems-on-chip (SoCs) calls for careful planning and organization, as well as flexible simulation technologies. Whether you are verifying a power-management … Read More

Mixed-Signal, IC Design

5 Jun, 2009
IC Design

DFM for Non-PhDs

Posted by David Abercrombie

David Abercrombie

I got a kick out of Rohan’s comment on my previous blog (How do you define DFM?).  It is too easy to assume that anyone knows what you are talking about when you say DFM.  Just because everyone has been talking about it doesn’t mean any of them know what they are talking about. You could probably infer from my approach to the previous blog that my background is primarily on the manufacturing side.

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IC Design, Yield, IC Verification, Design Quality, Reliability, Design for Manufacturing

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