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Posts tagged with 'IC Verification'

18 Mar, 2014
IC Design

Old Faithful

Posted by Shelly Stalnaker

Shelly Stalnaker While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More

IC Design, Foundry Solutions, IC Verification, 16nm, 20nm, 10nm, circuit, PERC, Reliability, electrical, 45nm, Verification, Calibre

19 Feb, 2014

Shelly Stalnaker The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the … Read More

IC Design, IC Verification, dynamic power grid analysis, vcd, vectorless verification, power grid analysis, value change dump

14 Feb, 2014
IC Design

Variability is EVERYWHERE!

Posted by Shelly Stalnaker

Shelly Stalnaker At advanced nodes, variability issues lurk behind every design mode, power state, process condition, and manufacturing step. Yet designers must find a way to balance the optimization of multiple operational modes and design corners against the aggressive performance and power targets demanded by today’s fast-moving markets. Concurrent analysis and optimization during place and route operations can provide … Read More

place and route, design corners, IC Design, concurrent analysis, Olympus-SoC, P&R, IC Verification, mcmm

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

15 Jan, 2014

Shelly Stalnaker DRC- and DFM-clean designs can still have hundreds to thousands of violations that must be debugged and corrected. How? Why? Mismatches between a router’s simplified tech file and the complete (and complex) signoff design rule decks at advanced nodes are generating significant numbers of DRC/DFM errors that can wreak havoc on your tapeout schedules. In particular, we’re seeing greater visibility … Read More

tech file, tapeout, DRC, Design Rule Checking, P&R, signoff, IC Design, IC Verification

20 Nov, 2009
IC Design

IBM Addresses Leakage

Posted by David Abercrombie

David Abercrombie

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield

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Physical Verification, Yield, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

20 Aug, 2009

David Abercrombie I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

4 Aug, 2009
IC Design

David's DAC09 - White Paper Session

Posted by David Abercrombie

David Abercrombie I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

31 Jul, 2009
IC Design

David's DAC09 - Another Special Guest

Posted by David Abercrombie

David Abercrombie Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More

Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules

28 Jul, 2009
IC Design

David's DAC09 - Off to a great start!

Posted by David Abercrombie

David Abercrombie Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More

IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

2 Jul, 2009
IC Design

To Waive Or Not To Waive?

Posted by David Abercrombie

David Abercrombie That is the question! If you read my colleague John’s most recent posting “Waive of the future?”, you will understand the question. I was equally shocked as John to find that almost no one tapes out DRC clean anymore. I would add one other reason to John’s list as to why this has happened. I think the traditional DRC rules are broken. Please read my first post “Are Design Rules Broken?” for my stance … Read More

IC Verification, IC Design, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

19 Jun, 2009

David Abercrombie One of the fundamental questions everyone asks about DFM is “why should I do it?” On the one hand this always strikes me as a funny question. I always look at DFM in the same way I think of automobile safety. Statistically, most people never get in a serious accident. So why would you spend so much money on airbags, antilock brakes, better seat belts, side door reinforcements, traction control, etc. … Read More

Yield, Design Quality, Design for Manufacturing, IC Verification, Reliability, Physical Verification, IC Design

5 Jun, 2009
IC Design

DFM for Non-PhDs

Posted by David Abercrombie

David Abercrombie

I got a kick out of Rohan’s comment on my previous blog (How do you define DFM?).  It is too easy to assume that anyone knows what you are talking about when you say DFM.  Just because everyone has been talking about it doesn’t mean any of them know what they are talking about. You could probably infer from my approach to the previous blog that my background is primarily on the manufacturing side.

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IC Design, Yield, IC Verification, Design Quality, Reliability, Design for Manufacturing

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