Mentor Blogs

Posts tagged with 'IDM'

Blogs RSS

28 Jan, 2010

Pattern Matching Might Solve World Hunger

Posted by Michael White

Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More

IDM, IC Design, Pattern Matching, SoC, eqDRC, Calibre, Fabless, Physical Verification, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite

IC Design

17 Dec, 2009

Does SVRF Direct Read Make Sense?

Posted by Michael White

Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More

Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, DRC, Sign-off, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC

Embedded Software

Simple measurements of software trace data using Sourcery Analyzer
Brad Dixon (Posted 5/22/13)
Open source components for your embedded platform SDK
Anil Khanna (Posted 5/21/13)
Book review [part 1]
Colin Walls (Posted 5/20/13)
All Blog Posts

Valor MSS PCB Manufacturing Systems Solutions

Where Is The Manufacturing World Coming To?
Michael Ford (Posted 5/16/13)
Retain your existing investment in assembly programs even if you change your machines
Mark Laing (Posted 5/14/13)
How do you manage your assembly variants?
Mark Laing (Posted 5/8/13)
All Blog Posts

Electrical & Wire Harness Design

A deep dive into automotive interface design
John Day (Posted 5/22/13)
Estimating wiring harness costs in seconds
John Day (Posted 5/9/13)
A pickup truck with park assist and a lot more
John Day (Posted 5/6/13)
All Blog Posts

FPGA

OVM Gets Connected
Dennis Brophy (Posted 9/10/12)
The floating point argument
Colin Walls (Posted 9/10/12)
Open Stand & EDA Standardization
Dennis Brophy (Posted 8/28/12)
All Blog Posts

Functional Verification

Part 1: The 2012 Wilson Research Group Functional Verification Study
Harry Foster (Posted 5/8/13)
Those nasty wire’s and reg’s in Verilog
Dave Rich (Posted 5/3/13)
Getting AMP’ed Up on the IEEE Low-Power Standard
Dennis Brophy (Posted 4/29/13)
All Blog Posts

IC Design

Battle of Fins and BOXes
Arvind Narayanan (Posted 12/7/12)
TSMC 28nm yield (SemiWiki)
Simon Favre (Posted 3/5/12)
DAC 2011 is upon us!
Simon Favre (Posted 5/11/11)
All Blog Posts

Mechanical Analysis

Why Not Just Shove a Heatsink on Top of it? Part 2: Heat Flow Budgets
Robin Bornoff (Posted 5/15/13)
Why Not Just Shove a Heatsink on Top of it? Part 1
Robin Bornoff (Posted 5/13/13)
Hot Off the Press
Nazita Saye (Posted 5/3/13)
All Blog Posts

PCB Design Software & Tools

PADS Tips and Tricks: Building a PCB Decal with Polar Patterns
Jim Martens (Posted 5/13/13)
Interactive Routing in the PADS ES Suite
Jim Martens (Posted 5/9/13)
Schematic Capture in the PADS ES Suite video release
Gary Lameris (Posted 5/3/13)
All Blog Posts

System Modeling

Engineering Muscle Memory
Mike Jensen (Posted 5/21/13)
EDA vs. Windows 8
Mike Jensen (Posted 5/6/13)
VHDL-AMS Stress Modeling – Part 3
Mike Jensen (Posted 3/25/13)
All Blog Posts

Vehicle System Design

U.S. DOT launches large V2V and V2I test
John Day (Posted 8/23/12)
Did you know this?
John Day (Posted 6/25/12)
Why aren’t tools from different suppliers easier to integrate?
John Day (Posted 6/19/12)
All Blog Posts

Aerospace and Military Solutions

To Infinity and Beyond
J VanDomelen (Posted 4/30/13)
Warp Factor 10, Mr. Sulu
J VanDomelen (Posted 4/25/13)
Bombardier Steps Up to the Big Boys
J VanDomelen (Posted 4/20/13)

Accelerating ARM-based Design

Instant Replay for Debugging SoC Level Simulations
Mark Olen (Posted 12/13/11)
GENIVI development strategy requires competitors to cooperate
John Day (Posted 11/10/11)
ARM Development Conference
Colin Walls (Posted 7/4/11)

Automotive Solutions

A deep dive into automotive interface design
John Day (Posted 5/22/13)
Estimating wiring harness costs in seconds
John Day (Posted 5/9/13)
A pickup truck with park assist and a lot more
John Day (Posted 5/6/13)

Foundry Solutions

How do you define DFM?
David Abercrombie (Posted 5/19/09)
Are Design Rules Broken?
David Abercrombie (Posted 5/15/09)

Rankingoptimierung said Thank you so much considerably intended for reveal... in ABV and people from Missouri...
Dave Rich said I know a few companies that have gone to the troub... in SystemVerilog Coding Guidelines
Linc Jepson said Dave, It's almost 4 years after this post. As fa... in SystemVerilog Coding Guidelines
simmons10 vigorda said What to Look for in a Hard Drive That You Are Purc... in Shortening Design Cycles With Concurrent Engineering
HMR said I am a bit worried some publications I have recent... in A Load of HVAC TLAs
Byron Blackmore said A project XML file will have a element, and an as... in FloTHERM and its new XML neutral file format
max lai said Heated Block Example Steel (Mild) 6.3000... in FloTHERM and its new XML neutral file format
max lai said Can "xml_case" tag makes it a project XML? becaus... in FloTHERM and its new XML neutral file format
max lai said Can tag makes it a project XML? because it seems ... in FloTHERM and its new XML neutral file format
Ramesh Sedam said Am very new to UVM and stuck with this error.. ple... in Using the UVM 1.0 Release with Questa

Mentor Blogs

Posts tagged with 'IDM'

Pattern Matching Might Solve World Hunger

Does SVRF Direct Read Make Sense?

Recent Comments

Tags

Blogs by Design Area

Mentor Blog Authors

The EDA Technology Leader™