IEEE Std. 1666™-2011 Available as Free Download
In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that … Read More
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
Tags: VMM, VIP-TSC, Accellera, IEEE, 1800, SystemVerilog, UVM, OVM, Standards
Historical Perspective
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and … Read More
Tags: VITAL, VHDL, VMM, IEEE, OVM, Accellera, UVM, UVM World, OVM World, Standards
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained … Read More
Tags: SystemVerilog, SystemC, TLM, 1800, Accellera, 1666, UVM, IEEE, OSCI, DAC, DATE
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But … Read More
Tags: SystemVerilog, SystemC, Verilog, 1076.4, 1364, 1076, VHDL, IP-XACT, Standards, VITAL, 1800, IEEE
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state … Read More
Tags: SystemC, esl, IEEE, 1666, OSCI, SoC, Jim Aynsley, Jim Hogan
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working … Read More
Tags: Standards, SystemVerilog, 1364, 1666, 1076, iec, TC93, Verilog, IEEE, 1800, VHDL, dual-logo, WG2
EDA & VLSI Standards Focus Meeting on 12 March 2010
As part of its continuing program to reach out to global technologists, the IEEE Standards Association will be conducting a series of outreach sessions throughout Bangalore from 10-12 March 2010. The IEEE-SA will also visit key governmental agencies in Delhi this week as well. While there is a focal technical point for each outreach session, the … Read More
Tags: IEEE 1800, IEEE-SA, IEEE, Standards, SystemVerilog
The SystemVerilog IEEE 1800-2009 Language Reference Manual (LRM) was published a few months ago with an unprecedented 472 updates. That’s in addition to the changes required as part of the merging process with the Verilog 1364-2005 LRM. And in that five year timeframe, the Mantis system that tracks all of the LRM issues has grown to 986 open issues, becoming a black hole for issues. The SystemVerilog … Read More
Tags: SystemVerilog, IEEE
No, this is not an early Olympics update.
But none the less, these three organizations have all earned 10’s. Thursday, 28 January 2010 at EDSFair, JEITA EDA-TC the Japan Electronics and Information Technology Industries Association’s standards group, celebrated their 10-year anniversary. The JEITA EDA-TC collaborates with the IEEE, Accellera and the Open SystemC Initiative. During the EDSFair … Read More
Tags: EDSFair, IEEE, Accellera, OSCI, Standards, IEEE-SA, JEITA
Jim Martens
Harry Foster
John Day
J VanDomelen
Paul Johnston
Robin Bornoff
Mike Jensen
Colin Walls
Jay Gorajia
Mark Olen
Travis Mikjaniec
Per Viklund