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Mentor Blogs

Posts tagged with 'OVM'

10 Nov, 2011

Dennis Brophy IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More

SystemC, TLM, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, UVM, OSCI, Verification Academy

13 Oct, 2011
Functional Verification

VHS or Betamax?

Posted by Dennis Brophy

Dennis Brophy Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

5 Oct, 2011

Dennis Brophy Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs.  The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011). Harry has been … Read More

VMM, VIP-TSC, Accellera, UVM, OVM

22 Jul, 2011

Dennis Brophy Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase.  New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it.  Everyone had their favorite VHDL book and I … Read More

VITAL, VHDL, VMM, OVM, Accellera, UVM, UVM World, OVM World

21 Apr, 2011

Dennis Brophy User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free.  U2U … Read More

Functional Verification, OVM, Accellera, UVM, VIP, U2U

25 Mar, 2011

Dennis Brophy Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

22 Feb, 2011

J VanDomelen The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More

UVM, Universal Verification Methodology, Milaero, Open Verification Methodology, OVM, TSC, Accellera, Mentor, IC, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP

28 Jan, 2011

Dennis Brophy Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support for … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

3 Dec, 2010

Harry Foster As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James. The goal of verification planning … Read More

Functional Verification, OVM, Assertion-Based Verification, Verification Methodology, UVM, Verification Academy

23 Sep, 2010

Dennis Brophy Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC).  Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate. As … Read More

OVM, ral, Accellera, UVM, VIP-TSC

10 Sep, 2010

Dennis Brophy Companion OVM Cookbook Examples Kit also offered for download Several months ago, the OVM Cookbook and the Examples Kit were made available for online use at the Verification Academy.  This proved to be a great help to accelerate the skill level of new OVM users.  Given the number of new projects that have deployed OVM and the number of new engineers that now need to use OVM, there is increased demand … Read More

OVM, Verification Academy, cookbook, Verification Methodology

7 Sep, 2010

Dennis Brophy Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently. Further, as part of the Accellera VIP-TSC UVM development … Read More

OVM, ral, Accellera, verification methodolgy, VIP-TSC, Register Package, UVM

28 Jun, 2010

Mark Glasser Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  … Read More

OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter

25 Jun, 2010

Harry Foster I’ve always loved the Chinese proverb, “Give a man a fish and you feed him for a day. Teach a man to fish and you feed him for a lifetime.” Yet, why merely settle for fish when you can have sushi! My point is, to remain strategically relevant in today’s competitive landscape, it is necessary to constantly reinvent ourselves and evolve our technical skills. To that end, we have created the Verification … Read More

OVM, Add new tag

9 Jun, 2010

Dennis Brophy DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA Cafe, click here. The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More

VMM, VIP, OVM, Accellera, verification IP, UVM

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