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Mentor Blogs

Posts tagged with 'Parasitic Extraction'

16 Jan, 2014
IC Design

FinFET Fever...or FinFET Fear?

Posted by Shelly Stalnaker

Shelly Stalnaker All the major foundries have announced FinFET technologies. FinFETs hold the promise of lower power usage and better area utilization, as well as traditional scaling improvements. Aaaaand…the thought of implementing them may be scaring the willies out of a lot of designers. How do I design these things? How do I know what the design needs? How do I verify them? Well, first, take a deep breath. … Read More

Parasitic Extraction, Foundry, transistor, 16nm, 22nm, 14nm, FinFET, Calibre, circuit design

13 Dec, 2013

Shelly Stalnaker While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. In this white paper from David Abercrombie, learn what multi-patterning is, why you need it, and how Calibre Multi-Patterning software … Read More

odd cycle, multipatterning, 16nm, Lithography, 20nm, mandrel, Mentor Graphics, Multi-Patterning, 14nm, colorless design, layout decomposition, D2S, LELE, anchor path, litho, Calibre Multi-Patterning, litho-etch-litho-etch, FinFET, double patterning, Foundry, warning rings, Parasitic Extraction, spacer-assisted, triple patterning, spacer is dielectric, spacer is mask, SID SADP, SIM SADP, pin coloring, pitch-split

20 May, 2009

Karen Chow Hi everyone, and welcome to my first blog entry. When I found out that I was going to be writing a blog on parasitic extraction, my first thoughts were: Blog = fun, edgy, exciting Parasitic extraction = geeky, techie, boring Therefore, Blog ≠ Parasitic Extraction How was I going to make this work? How am I going to make model order reduction and stochastic integral equation solvers and nanometer … Read More

Parasitic Extraction, Calibre

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