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Posts tagged with 'PCI Express'

21 Jan, 2013

Randall Myers

After years of pooh-poohing AMD, Intel had to admit you could get more data throughput switching to a high-speed serial approach. Let’s say high-speed serial is in the 1 to 10 Gbps range per lane, and use PCIe as an example. This is where the benefits become irresistible and the behavior becomes unexpected according to the previous rules of layout design. The PCIe specification helps define the different

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RF, Signal Integrity, PCI Express

3 Nov, 2011
PCB Design

Stupid vias... {grumble grumble}

Posted by Patrick Carrier

Patrick Carrier

Yeah, I can totally see Homer Simpson designing his SERDES bus and getting frustrated by all the additional insertion loss caused by his vias, and muttering to himself, “Stupid vias…” and grumbling.  And then going into the lab, looking at his failing eye diagram, and shouting “D’oh!”.  Okay, well Homer Simpson probably won’t be designing any SERDES busses anytime

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DDRx, Signal Integrity, PCI Express

2 Nov, 2011

Patrick Carrier

The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running. When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential

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PCI Express, Signal Integrity, SERDES

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