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Mentor Blogs

Posts tagged with 'Physical Verification'

29 Jan, 2014

Shelly Stalnaker Download the latest version of our guide to multi-patterning design and debugging, containing links to all of David Abercrombie’s detailed educational articles on SemiEngineering.com, along with links for complementary reference and learning options. Whether you are already working on designs with multi-patterning requirements, or just beginning multi-patterning work, you will benefit from David’s … Read More

triple patterning, double patterning, IC Design, Debugging, Physical Verification, SADP, ic manufacturing, Multi-Patterning

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

15 Jan, 2014
IC Design

How Do I?

Posted by Shelly Stalnaker

Shelly Stalnaker It happens all the time, to all of us. You need a quick answer for a very specific question about using your EDA tools. You don’t want to wade through technical documentation, you don’t have time for an email response, and you really don’t want to try searching EDA forums for an answer. We feel your pain, and we decided to do something about it. Need to know how to extract a net from … Read More

tapeout, Debugging, Calibre, Productivity, signoff, electrical verification, Physical Verification

2 Jun, 2010
IC Design

Enabling Superior Support

Posted by John Ferguson

John Ferguson In my last few posts, I began discussing on what it takes to enable software quality and support.  This particular post will focus on the latter, support. Of course the goal of any descent software provider is to deliver software that is bug free, intuitive to use, and performs a valuable service.  While we strive for perfection, in reality these goals can never be fully achieved.  In the EDA world, … Read More

Mentor Graphics, Physical Verification, Calibre, Support

27 Jan, 2010
IC Design

The Value of Support

Posted by John Ferguson

John Ferguson When asked about the value that the Calibre platform brings to the design community, most folks will respond with performance, foundry support, and ease of debugging. While these are all valuable aspects and traits of Calibre, there is one more benefit that is often taken for granted: support. The word “support” is something bandied around loosely in EDA. Saying you have good support is akin to saying … Read More

DRC, EDA Ssoftware Support, Calibre, LVS, Physical Verification

15 Dec, 2009

John Ferguson I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight. Tezzaron Semiconductor … Read More

Deepchip, DRC, Calibre, Quartz, Tezzaron, LVS, Physical Verification

20 Nov, 2009
IC Design

IBM Addresses Leakage

Posted by David Abercrombie

David Abercrombie

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield

Read More

Physical Verification, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

30 Sep, 2009
IC Design

The Biggest Loser?

Posted by John Ferguson

John Ferguson A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More

DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV

20 Aug, 2009

David Abercrombie I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

6 Aug, 2009
IC Design

David's DAC09 - Lunch & Learn

Posted by David Abercrombie

David Abercrombie My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP. It started … Read More

Design Quality, Design for Manufacturing, IP, Physical Verification

4 Aug, 2009
IC Design

David's DAC09 - White Paper Session

Posted by David Abercrombie

David Abercrombie I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

31 Jul, 2009
IC Design

David's DAC09 - Another Special Guest

Posted by David Abercrombie

David Abercrombie Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More

Reliability, IC Verification, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules

28 Jul, 2009
IC Design

David's DAC09 - Off to a great start!

Posted by David Abercrombie

David Abercrombie Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More

IC Verification, IC Design, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

21 Jul, 2009
IC Design

Waive Bye-Bye

Posted by John Ferguson

John Ferguson In my last post I discussed the reasons and challenges associated with “waivers” for DRC.  As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex.  To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage.  Not only is the DRC debug … Read More

Physical Verification, DRC, Calibre, DAC, Waivers

2 Jul, 2009
IC Design

To Waive Or Not To Waive?

Posted by David Abercrombie

David Abercrombie That is the question! If you read my colleague John’s most recent posting “Waive of the future?”, you will understand the question. I was equally shocked as John to find that almost no one tapes out DRC clean anymore. I would add one other reason to John’s list as to why this has happened. I think the traditional DRC rules are broken. Please read my first post “Are Design Rules Broken?” for my stance … Read More

IC Verification, IC Design, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

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