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Mentor Blogs

Posts tagged with 'Physical Verification'

29 Jan, 2014

Shelly Stalnaker Download the latest version of our guide to multi-patterning design and debugging, containing links to all of David Abercrombie’s detailed educational articles on SemiEngineering.com, along with links for complementary reference and learning options. Whether you are already working on designs with multi-patterning requirements, or just beginning multi-patterning work, you will benefit from David’s … Read More

triple patterning, double patterning, IC Design, Debugging, Physical Verification, SADP, ic manufacturing, Multi-Patterning

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

15 Jan, 2014
IC Design

How Do I?

Posted by Shelly Stalnaker

Shelly Stalnaker It happens all the time, to all of us. You need a quick answer for a very specific question about using your EDA tools. You don’t want to wade through technical documentation, you don’t have time for an email response, and you really don’t want to try searching EDA forums for an answer. We feel your pain, and we decided to do something about it. Need to know how to extract a net from … Read More

tapeout, Debugging, Calibre, Productivity, signoff, electrical verification, Physical Verification

2 Jun, 2010
IC Design

Enabling Superior Support

Posted by John Ferguson

John Ferguson In my last few posts, I began discussing on what it takes to enable software quality and support.  This particular post will focus on the latter, support. Of course the goal of any descent software provider is to deliver software that is bug free, intuitive to use, and performs a valuable service.  While we strive for perfection, in reality these goals can never be fully achieved.  In the EDA world, … Read More

Mentor Graphics, Physical Verification, Calibre, Quality, Support

30 Mar, 2010

Michael White In both my last post, and in John Ferguson’s posts, the reasons, challenges and costs associated with “waivers” for DRC were discussed.  As we have both pointed out, this is a growing problem as the IC industry increases its use of 3rd party IP while simultaneously the number of waivers within that IP is also increasing – resulting in a sea of waivers to deal with.  As we have deployed our Calibre … Read More

Waiver, Fab-lite, Fabless, Calibre, IC Design, Physical Verification, Foundries, Foundry

28 Jan, 2010

Michael White Design rule checking (DRC) or physical verification used to be easy.  For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go.  These checks were simple to write, fast to run and understandable, and quick to debug.  Today is a new world order, where none of these attributes are true anymore.  An increasing number of checks are 2-D, very … Read More

IDM, IC Design, Pattern Matching, SoC, eqDRC, Calibre, Physical Verification, Fabless, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite

27 Jan, 2010
IC Design

The Value of Support

Posted by John Ferguson

John Ferguson When asked about the value that the Calibre platform brings to the design community, most folks will respond with performance, foundry support, and ease of debugging. While these are all valuable aspects and traits of Calibre, there is one more benefit that is often taken for granted: support. The word “support” is something bandied around loosely in EDA. Saying you have good support is akin to saying … Read More

DRC, EDA Ssoftware Support, Calibre, LVS, Physical Verification

15 Jan, 2010

Michael White Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass.  Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out.  Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC

17 Dec, 2009

Michael White Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More

Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, Sign-off, DRC, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC

15 Dec, 2009

John Ferguson I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight. Tezzaron Semiconductor … Read More

Deepchip, DRC, Calibre, Quartz, Tezzaron, LVS, Physical Verification

20 Nov, 2009
IC Design

IBM Addresses Leakage

Posted by David Abercrombie

David Abercrombie

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield

Read More

Physical Verification, Yield, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

30 Sep, 2009
IC Design

The Biggest Loser?

Posted by John Ferguson

John Ferguson A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More

DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV

20 Aug, 2009

David Abercrombie I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

6 Aug, 2009
IC Design

David's DAC09 - Lunch & Learn

Posted by David Abercrombie

David Abercrombie My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP. It started … Read More

Design Quality, Design for Manufacturing, IP, Physical Verification, Yield

4 Aug, 2009
IC Design

David's DAC09 - White Paper Session

Posted by David Abercrombie

David Abercrombie I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

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