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Posts tagged with 'place and route'

13 May, 2014

Shelly Stalnaker With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased … Read More

P&R, Olympus-SoC, place and route, 16nm, 20nm, 10nm, IC Design, Multi-Patterning, double patterning, FinFET

14 Mar, 2014
IC Manufacturing

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

14 Feb, 2014
IC Design

Variability is EVERYWHERE!

Posted by Shelly Stalnaker

Shelly Stalnaker At advanced nodes, variability issues lurk behind every design mode, power state, process condition, and manufacturing step. Yet designers must find a way to balance the optimization of multiple operational modes and design corners against the aggressive performance and power targets demanded by today’s fast-moving markets. Concurrent analysis and optimization during place and route operations can provide … Read More

place and route, design corners, IC Design, concurrent analysis, Olympus-SoC, P&R, IC Verification, mcmm

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