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Mentor Blogs

Posts tagged with 'SERDES'

3 Jul, 2013

Patrick Carrier When designing a PCB, part of the design process is making sure the PCB works correctly.  At the very least, someone does some functional testing.  But what happens if problems are found?  A more detailed look at the design must be performed.  And in fact, the best way to end up with a working design is to check the performance during the design process. So if you have to choose between simulating or … Read More

SERDES

26 Jun, 2013
PCB Design

Simulation and measurement

Posted by Patrick Carrier

Patrick Carrier A few months ago my colleague Chuck Ferry posted a blog about a correlation study he did for DesignCon, where he compared results from a multi-Gbs SERDES simulation to some measured results and showed excellent correlation.  If you are interested, scroll down and you can find that blog, or you can click on this link: http://blogs.mentor.com/hyperblog/blog/2013/02/07/developing-confidence-in-your-analysis-tool-hyperlynx-9-0-demonstration/. Correlating … Read More

SERDES

4 Jan, 2013

Patrick Carrier

In the past I have blogged about crossing splits in reference planes.  This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.  But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via.  In such a case, the reference planes will change and

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DDRx, SERDES

12 Jul, 2012

Zhen Mu

For SERDES channel designs, board/system designers are told to remove stubs and non-functional pads (NFP) of vias on channels to ensure signal quality at the receiver ends. What confuses them the most is when to consider these effects: does one have to remove all NFPs and stubs in any channel carrying signals with data rates over 1Gbps? Can a design still work even if via stubs are kept? The actual

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SERDES

11 Jul, 2012

Zhen Mu

  Designers dealing with SERDES channels pay more and more attention to signal via effects. Many literatures and guidelines talk about the approaches to correctly configure vias so that via effects on signals can be minimized. Such methods require detailed analysis of single via or differential via pair. With the help of accurate 3D field solvers, vias can be designed to have controlled noise in channels

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3DEM simulation, SERDES

23 May, 2012
PCB Design

Need stitching vias?

Posted by Zhen Mu

Zhen Mu

When trying to design SERDES signals on board, designers often receive recommendations on placing stitching vias around differential signal vias of a channel. The purpose is to provide continuous return current path when signals switch layers, so that the discontinuity of trace impedance can be minimized. Because of the increasing board density, the issues designers are facing by following this recommendation

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SERDES

1 May, 2012
PCB Design

Crosstalk is everywhere

Posted by Patrick Carrier

Patrick Carrier

Crosstalk is everywhere.  Really, in a more general sense, noise coupling is everywhere.  Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields.  This most often occurs on PCB designs with dense routing, and on wide parallel busses.  Even on newer SERDES busses, however, it is still

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crosstalk, SERDES

7 Mar, 2012
PCB Design

The Parallel Pain

Posted by Patrick Carrier

Patrick Carrier

Parallel busses are a pain to implement.  They really are.  Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems.  SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems.  Parallel busses are single-ended, so they tend to draw a lot more power.  So that means you

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SERDES

6 Mar, 2012

Patrick Carrier

Interconnect loss modeling?  Check.  Signal conditioning modeling?  Check.  Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?  Oooh…. that’s a tough one.  Check! Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?  Wow!  Check. 3D

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S-parameter, crosstalk, SERDES

5 Mar, 2012
PCB Design

Know your limits

Posted by Patrick Carrier

Patrick Carrier

“A man’s got to know his limitations” … true, and so does a digital bus.  Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses.  Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity.  And now, in sharp contrast, we’ve progressed to the point where

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SERDES, DDRx, BER

30 Jan, 2012

Per Viklund

Do you remember the hype on EP’s (Embedded Passives) just a few years ago? In the PCBD&F magazine, late in 2006, Kathy Nargi-Toth wrote in an Editorial to PCD&F referring to an industry survey: The statistic that blew me away was the change in anticipated implementation of embedded passives. The projections are that 24.6% of the PCBs, up 222% over current figures, will incorporate embedded components. 

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SERDES, RF, Embedded passives

4 Nov, 2011
PCB Design

Shorter stubs are getting longer

Posted by Patrick Carrier

Patrick Carrier

…It all depends on how fast you are trying to go.  That’s really the name of the game with anything signal integrity.  The faster we go, the more “new” problems we face.  Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal. At the beginning of my

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SERDES

2 Nov, 2011

Patrick Carrier

The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running. When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential

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PCI Express, SERDES

14 Jan, 2011

Patrick Carrier

In the digital design world, we have typically only seen S-parameters used to model packages.  They are a popular output of 3D field solvers like IE3D.  But more and more, especially in SERDES design, we are seeing S-parameters being used for a variety of parts.  One of the reasons for their growing popularity is their fater simulation time, especially when advanced simulation techniques are used, as

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SERDES

12 Jan, 2011

Patrick Carrier

Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model.  Hours.  Sometimes you have to kick it off overnight.  And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims.  I mean, you could take the time that your sim is running to

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