In the past I have blogged about crossing splits in reference planes. This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.
But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via. In such a case, the reference planes will change and … Read More
Mentor Blogs
Posts tagged with 'SERDES'
For SERDES channel designs, board/system designers are told to remove stubs and non-functional pads (NFP) of vias on channels to ensure signal quality at the receiver ends. What confuses them the most is when to consider these effects: does one have to remove all NFPs and stubs in any channel carrying signals with data rates over 1Gbps? Can a design still work even if via stubs are kept?
The actual … Read More
Designers dealing with SERDES channels pay more and more attention to signal via effects. Many literatures and guidelines talk about the approaches to correctly configure vias so that via effects on signals can be minimized. Such methods require detailed analysis of single via or differential via pair. With the help of accurate 3D field solvers, vias can be designed to have controlled noise in channels … Read More
When trying to design SERDES signals on board, designers often receive recommendations on placing stitching vias around differential signal vias of a channel. The purpose is to provide continuous return current path when signals switch layers, so that the discontinuity of trace impedance can be minimized.
Because of the increasing board density, the issues designers are facing by following this recommendation … Read More
Crosstalk is everywhere. Really, in a more general sense, noise coupling is everywhere. Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields. This most often occurs on PCB designs with dense routing, and on wide parallel busses. Even on newer SERDES busses, however, it is still … Read More
Parallel busses are a pain to implement. They really are. Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems. SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems. Parallel busses are single-ended, so they tend to draw a lot more power. So that means you … Read More
Interconnect loss modeling? Check.
Signal conditioning modeling? Check.
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain? Oooh…. that’s a tough one. Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis? Wow! Check.
3D … Read More
“A man’s got to know his limitations” … true, and so does a digital bus. Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses. Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity. And now, in sharp contrast, we’ve progressed to the point where … Read More
Do you remember the hype on EP’s (Embedded Passives) just a few years ago?
In the PCBD&F magazine, late in 2006, Kathy Nargi-Toth wrote in an Editorial to PCD&F referring to an industry survey:
The statistic that blew me away was the change in anticipated implementation of embedded passives.
The projections are that 24.6% of the PCBs, up 222% over current figures, will incorporate embedded … Read More
…It all depends on how fast you are trying to go. That’s really the name of the game with anything signal integrity. The faster we go, the more “new” problems we face. Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal.
At the beginning of my … Read More
The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running.
When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential … Read More
In the digital design world, we have typically only seen S-parameters used to model packages. They are a popular output of 3D field solvers like IE3D. But more and more, especially in SERDES design, we are seeing S-parameters being used for a variety of parts. One of the reasons for their growing popularity is their fater simulation time, especially when advanced simulation techniques are used, as … Read More
Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model. Hours. Sometimes you have to kick it off overnight. And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims. I mean, you could take the time that your sim is running to … Read More
Intersil has a long if somewhat convoluted history in the semiconductor business but for the past few years it’s kept a relatively low profile in automotive electronics. That may be changing.
At Convergence in October Intersil announced a lithium-ion battery management system (ISL 78600) and safety monitor (ISL 78601). More recently it introduced a serializer/deserializer (SerDes) transceiver (ISL … Read More
lithium ion battery management system, National, Intersil, serializer/deserializer, National Semiconductor, SERDES
If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface. AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers. Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More
-
SEP 2.0
Colin Walls (Posted 6/17/13) -
How to make use of Android on Linux IVI systems with Linux Containers
Kamran Shah (Posted 6/12/13) -
Device Firmware Upgrade through USB
Colin Walls (Posted 6/10/13) - All Blog Posts
-
New PADS Website and Webinar
Jim Martens (Posted 6/11/13) -
Selective Autorouting to Increase Productivity
Jim Martens (Posted 6/5/13) -
What’s New with PADS?
Jim Martens (Posted 6/3/13) - All Blog Posts
-
Do you use Boundary Scan in your PCB assembly process?
Mark Laing (Posted 6/11/13) -
Juki ISS Interface, now improved
Mark Laing (Posted 5/31/13) -
Where Is The Manufacturing World Coming To?
Michael Ford (Posted 5/16/13) - All Blog Posts
-
Help me find a parking space
John Day (Posted 6/14/13) -
A truck transformed
John Day (Posted 6/9/13) -
The massive growth of automotive electronics
John Day (Posted 5/30/13) - All Blog Posts
-
OVM Gets Connected
Dennis Brophy (Posted 9/10/12) -
The floating point argument
Colin Walls (Posted 9/10/12) -
Open Stand & EDA Standardization
Dennis Brophy (Posted 8/28/12) - All Blog Posts
-
Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
Tom Fitzpatrick (Posted 5/31/13) -
IEEE 1801™-2013 UPF Standard Is Published
Dennis Brophy (Posted 5/29/13) -
Part 1: The 2012 Wilson Research Group Functional Verification Study
Harry Foster (Posted 5/8/13) - All Blog Posts
-
Battle of Fins and BOXes
Arvind Narayanan (Posted 12/7/12) -
TSMC 28nm yield (SemiWiki)
Simon Favre (Posted 3/5/12) -
DAC 2011 is upon us!
Simon Favre (Posted 5/11/11) - All Blog Posts
-
Why Not Just Shove a Heatsink on Top of it? Part 2: Heat Flow Budgets
Robin Bornoff (Posted 5/15/13) -
Why Not Just Shove a Heatsink on Top of it? Part 1
Robin Bornoff (Posted 5/13/13) -
Hot Off the Press
Nazita Saye (Posted 5/3/13) - All Blog Posts
-
SystemVision 5.10
Mike Jensen (Posted 6/5/13) -
Engineering Muscle Memory
Mike Jensen (Posted 5/21/13) -
EDA vs. Windows 8
Mike Jensen (Posted 5/6/13) - All Blog Posts
-
U.S. DOT launches large V2V and V2I test
John Day (Posted 8/23/12) -
Did you know this?
John Day (Posted 6/25/12) -
Why aren’t tools from different suppliers easier to integrate?
John Day (Posted 6/19/12) - All Blog Posts
-
Lofty Goals Part One
J VanDomelen (Posted 5/30/13) -
Coming Soon to a TV Near You
J VanDomelen (Posted 5/29/13) -
To Infinity and Beyond
J VanDomelen (Posted 4/30/13)
-
Instant Replay for Debugging SoC Level Simulations
Mark Olen (Posted 12/13/11) -
GENIVI development strategy requires competitors to cooperate
John Day (Posted 11/10/11) -
ARM Development Conference
Colin Walls (Posted 7/4/11)
-
Help me find a parking space
John Day (Posted 6/14/13) -
A truck transformed
John Day (Posted 6/9/13) -
The massive growth of automotive electronics
John Day (Posted 5/30/13)
-
How do you define DFM?
David Abercrombie (Posted 5/19/09) -
Are Design Rules Broken?
David Abercrombie (Posted 5/15/09)
Recent Comments
- Tiffiny said Amazing! This blog looks just like my old one! It'... in Part 1: The 2010 Wilson Research Group Functional Verification Study
- paulo luiz said Hi Robin Thanks for your clarification. I used the... in Thermal Design Perfection Starts with the use of FloTHERM PACK
- Robin Bornoff said Rjb is experimentally measured as defined the the ... in Thermal Design Perfection Starts with the use of FloTHERM PACK
- paulo luiz said The thermal resistance from junction to board (Rjb... in Thermal Design Perfection Starts with the use of FloTHERM PACK
- prabhu_k said hi dave, i am trying to stimulate questasim 10.1... in Using the UVM 1.0 Release with Questa
- Dave Rich said The functionality of uvm_container merged into UV... in An Extension to UVM: The UVM Container
- Dave Rich said I know a few companies that have gone to the troub... in SystemVerilog Coding Guidelines
- Linc Jepson said Dave, It's almost 4 years after this post. As fa... in SystemVerilog Coding Guidelines
- simmons10 vigorda said What to Look for in a Hard Drive That You Are Purc... in Shortening Design Cycles With Concurrent Engineering
Tags
Blogs by Design Area
- Embedded Software
- PCB Design
- Valor MSS PCB Manufacturing Systems Solutions
- Electrical & Wire Harness Design
- FPGA
- Functional Verification
- IC Design
- Mechanical Analysis
- System Modeling
- Vehicle System Design