Mentor Blogs

In the past I have blogged about crossing splits in reference planes.  This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.  But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via.  In such a case, the reference planes will change and … Read More

DDR3, DDR4, SERDES

For SERDES channel designs, board/system designers are told to remove stubs and non-functional pads (NFP) of vias on channels to ensure signal quality at the receiver ends. What confuses them the most is when to consider these effects: does one have to remove all NFPs and stubs in any channel carrying signals with data rates over 1Gbps? Can a design still work even if via stubs are kept? The actual … Read More

SERDES

  Designers dealing with SERDES channels pay more and more attention to signal via effects. Many literatures and guidelines talk about the approaches to correctly configure vias so that via effects on signals can be minimized. Such methods require detailed analysis of single via or differential via pair. With the help of accurate 3D field solvers, vias can be designed to have controlled noise in channels … Read More

3D field solver, SERDES

Crosstalk is everywhere.  Really, in a more general sense, noise coupling is everywhere.  Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields.  This most often occurs on PCB designs with dense routing, and on wide parallel busses.  Even on newer SERDES busses, however, it is still … Read More

SERDES, crosstalk

Parallel busses are a pain to implement.  They really are.  Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems.  SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems.  Parallel busses are single-ended, so they tend to draw a lot more power.  So that means you … Read More

SERDES

Interconnect loss modeling?  Check.  Signal conditioning modeling?  Check.  Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?  Oooh…. that’s a tough one.  Check! Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?  Wow!  Check. 3D … Read More

crosstalk, SERDES, 3D via, S-parameter

“A man’s got to know his limitations” … true, and so does a digital bus.  Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses.  Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity.  And now, in sharp contrast, we’ve progressed to the point where … Read More

SERDES, DDRx, BER

Do you remember the hype on EP’s (Embedded Passives) just a few years ago? In the PCBD&F magazine, late in 2006, Kathy Nargi-Toth wrote in an Editorial to PCD&F referring to an industry survey: The statistic that blew me away was the change in anticipated implementation of embedded passives. The projections are that 24.6% of the PCBs, up 222% over current figures, will incorporate embedded … Read More

SERDES, RF, Embedded passives

…It all depends on how fast you are trying to go.  That’s really the name of the game with anything signal integrity.  The faster we go, the more “new” problems we face.  Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal. At the beginning of my … Read More

SERDES, via

The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running. When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential … Read More

via, PCI Express, SERDES

In the digital design world, we have typically only seen S-parameters used to model packages.  They are a popular output of 3D field solvers like IE3D.  But more and more, especially in SERDES design, we are seeing S-parameters being used for a variety of parts.  One of the reasons for their growing popularity is their fater simulation time, especially when advanced simulation techniques are used, as … Read More

SERDES

You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation.  IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface.  These models are an addendum to the existing IBIS spec that contain executable models.  Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model.  The executable … Read More

SPICE, Fasteye, SERDES, IBIS, IBIS-AMI

Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model.  Hours.  Sometimes you have to kick it off overnight.  And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims.  I mean, you could take the time that your sim is running to … Read More

SPICE, SERDES

Intersil has a long if somewhat convoluted history in the semiconductor business but for the past few years it’s kept a relatively low profile in automotive electronics. That may be changing. At Convergence in October Intersil announced a lithium-ion battery management system (ISL 78600) and safety monitor (ISL 78601). More recently it introduced a serializer/deserializer (SerDes) transceiver (ISL … Read More

lithium ion battery management system, National, Intersil, serializer/deserializer, National Semiconductor, SERDES

If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface.   AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers.   Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More

IBIS, SERDES