Mentor Blogs

A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables … Read More

Functional Verification, Instant Replay, Emulation, Verification, Verification Academy, JTAG, SoC

I was involved in a discussion about driver workload management the other week. It is a fascinating topic and I can see it becoming a much more important feature of in-vehicle HMIs in the coming years. The basic concept is pretty straightforward – when a driver is in a high workload situation (e.g. driving at 70mph on a crowded freeway), the HMI adapts so that the functionality available to the driver … Read More

CAN/LIN, Medical, Energy, Freescale, Ethernet, Infotainment, MOST, Automotive, IVI, SoC, flexray

Today, more ‘things’ are connected to the Internet than there are people on the planet. Connectivity was a major theme at last week’s Freescale FTF event in San Antonio, Texas. There were over 1300 attendees, and around 200 technical sessions over the course of 4 days. An impressive range of SoC solutions aimed at connectivity covered such diverse applications, from Medical, Energy Management, Safety … Read More

IVI, Infotainment, Medical, CAN/LIN, Automotive, MOST, flexray, Freescale, SoC, Energy, Ethernet

Is my car trying to tell me something? This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More

UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing multiple replays of events in question … Read More

Verification, testbench, SoC Level Verification, Cortex, ARM, Software as a Testbench, Functional Verification, SoC

Watch DVCon Co-Located Event Presentations Two presentations from the second annual SystemC Day at DVCon 2011 are available now.  The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos.  SystemC Day brought users together to discuss the current state … Read More

SystemC, esl, 1666, OSCI, SoC, Jim Aynsley, Jim Hogan

Welcome to part two of my four-part (part one) ESC 2010 blog series. Today’s topic: shifts in the industry. One of the biggest trends I observed at the show was the start of a paradigm shift in the evolution of Electronic Design Automation (EDA) software companies and their products. EDA software companies have traditionally provided the software tools and services to create modern day semiconductors, … Read More

OS, Operating System, middleware, Android, app, Mil-Aero, Milaero, Military, Aerospace, drivers, Mentor, Mentor Graphics, app-driven, Mentor.com, apps, Google, Engineer, Hardware, SoC, System on Chip, Software, soldier

This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More

Redundancy, CAA, SoC, SRAM

Design rule checking (DRC) or physical verification used to be easy.  For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go.  These checks were simple to write, fast to run and understandable, and quick to debug.  Today is a new world order, where none of these attributes are true anymore.  An increasing number of checks are 2-D, very … Read More

IDM, IC Design, Pattern Matching, SoC, eqDRC, Calibre, Fabless, Physical Verification, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite

Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass.  Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out.  Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC