Posted Feb 21, 2012, by Dennis Brophy
Is my car trying to tell me something?
This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA). (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More
Tags:
UVM,
Tipping Point,
Veloce,
inFact,
Intelligent Testbench Automation,
Crossing the Chasam,
Questa,
SoC,
iTBA,
OVM
Posted Dec 13, 2011, by Mark Olen
Instant Replay Offers Multiple Views at Any Speed
If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time. But watching at home on television, we get the luxury of viewing multiple replays of events in question … Read More
Tags:
Verification,
testbench,
Cortex,
Functional Verification,
ARM,
SoC Level Verification,
Software as a Testbench,
SoC
Posted Apr 15, 2011, by Dennis Brophy
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state … Read More
Tags:
SystemC,
esl,
1666,
OSCI,
SoC,
Jim Aynsley,
Jim Hogan
Posted May 12, 2010, by J VanDomelen
Welcome to part two of my four-part (part one) ESC 2010 blog series. Today’s topic: shifts in the industry. One of the biggest trends I observed at the show was the start of a paradigm shift in the evolution of Electronic Design Automation (EDA) software companies and their products.
EDA software companies have traditionally provided the software tools and services to create modern day semiconductors, … Read More
Tags:
OS,
Operating System,
middleware,
Android,
app,
Mil-Aero,
Milaero,
Military,
Aerospace,
drivers,
Mentor,
EDA,
Mentor Graphics,
app-driven,
Mentor.com,
apps,
Google,
Engineer,
Hardware,
SoC,
System on Chip,
Software,
soldier
Posted May 11, 2010, by Simon Favre
This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More
Tags:
Redundancy,
CAA,
SoC,
SRAM
Posted Jan 28, 2010, by Michael White
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
Tags:
IDM,
IC Design,
Pattern Matching,
EDA,
SoC,
eqDRC,
Calibre,
Fabless,
Physical Verification,
Productivity,
Foundries,
Equation-Based DRC,
PV,
Sign-off,
Fab-lite
Posted Jan 15, 2010, by Michael White
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags:
Foundry,
Foundries,
IC Design,
DRC,
SVRF,
EDA,
Tax,
Waiver,
Calibre,
Physical Verification,
Fab-lite,
Productivity,
Fabless,
Sign-off,
eqDRC,
SoC,
Equation-Based DRC
Posted Oct 7, 2009, by Ralph Zak
Transaction-Based Verification is a technique for verifying modern SoC designs with interfaces such as PCI express, using test benches at the transaction level of abstraction. Transaction-based verification complements directed and constrained random tests, and is an emerging methodology for verifying complex SoCs that have multiple on-chip standard bus and peripheral interfaces. Typically in a transaction-based … Read More
Tags:
TBV,
System on Chip,
Transaction-Based Verification,
Emulation,
FPGA Prototyping,
ASIC Emulation,
SoC,
SoC Verification,
Simulation Server Farms
Posted Jul 20, 2009, by Ralph Zak
This is my first blog posting about SoC Emulation for verification of SoC designs. To set the stage, along with my biases, I am currently employed by Mentor Graphics and responsible for business development in the Emulation Division. I am an un-apologetic, evangelist for hardware-based verification.
My experiences with hardware assisted verification began with simulation accelerators in the 80’s … Read More
Tags:
SoC Prototyping,
SoC Emulation,
ASIC Emulation,
ASIC Verification,
EDA,
Prototyping,
SoC,
FPGA Boards,
FPGA Prototyping