You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation. IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface. These models are an addendum to the existing IBIS spec that contain executable models.
Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model. The executable … Read More
Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model. Hours. Sometimes you have to kick it off overnight. And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims. I mean, you could take the time that your sim is running to … Read More
I like martial arts films, from the old black and white movies dubbed in English or even subtitled, to the modern blockbusters with their almost endless array of special effects. I admit that I can’t really tell the different martial art styles apart, but frankly I don’t need to. Being able to distinguish styles wouldn’t add to my enjoyment of the films. What I do enjoy is watching a skilled expert (even … Read More
Tags: SPICE
Working with customers is one of the great pleasures of my job. Whether in a meeting or at a tradeshow, it’s always fun to chat with engineers to see how they use simulation in their design flows – and maybe use the opportunity to discuss how SystemVision might help their design processes. Among my favorite interactions with customers, however, is teaching simulation and modeling training classes.
Mentor … Read More
Tags: SPICE
School is out. Has been for a few weeks. And the end of every school year brings the usual rush of awards assemblies, especially in junior high and elementary schools. This year was no different. But let me first give you a little background into why we found this year’s awards assembly a little…well…strange.
I am the designated math tutor in my house. Yet another benefit – or perhaps implied responsibility … Read More
Tags: SPICE, Mechatronic
I remember my early days in the EDA industry. SPICE was little more than a teenager (I suppose this dates me a bit). I had recently finished a 5-year stint working for the United States Air Force and had just joined a young company as an Applications Engineer to help promote the features and benefits of system design using Hardware Description Languages (HDLs). Though HDL use for semiconductor design … Read More
Tags: SPICE, HDL, IEEE 1076.1, EDA, Multi-Level Design, Mechatronic, Mixed-Signal
If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface. AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers. Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More
Tags: Multi-Gigabit, Models, SERDES, ATM, Xilinx, Eye Diagram, AMI, IBIS 5.0, SPICE, V5, Modeling, HyperLynx, Virtex 5, Webinar, IBIS
DesignCon is coming up in less than a month, February 1-4 in Santa Clara, CA (find your way to San Jose and turn left). This is a great show, and we at Mentor have put together some great sessions for you; and we have more than just technical content, we have some fun plans as well.
One of those fun things is a panel called “Science Fiction: Is It Really Fiction” Tuesday, February 2nd from 3:45 … Read More
Lumped block package representation makes the best use of limited available data to simulate for an ‘indication’ of case temperature. Some indication is better than none but I wouldn’t bet on it, really, I wouldn’t. Accurate case and junction temperature prediction can only be realised with either a fully 3D detailed representation or an abstracted CTM (compact thermal model) representation. Here we’ll … Read More
Tags: Thermal Resistor, CTM, Electronics Cooling, Component, SPICE, Thermal Resistance, IBIS
Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future…
Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout … Read More
Tags: Verilog, SPICE, Calibre_LVS, Hierarchical LVS, Calibre, Netlist, nmLVS, Hierarchical_LVS, LVS
Jim Martens
John Day
J VanDomelen
Nazita Saye
Michael Ford
Colin Walls
Tom Fitzpatrick
Mark Laing
Zhen Mu
Travis Mikjaniec
Christopher Hallinan
Bernard Sutton