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Posts tagged with 'SVRF'

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15 Jan, 2010

Stop Paying the DRC Waiver Productivity Tax

Posted by Michael White

Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC

IC Design

17 Dec, 2009

Does SVRF Direct Read Make Sense?

Posted by Michael White

Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More

Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, DRC, Sign-off, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC

Embedded Software

Book review [part 1]
Colin Walls (Posted 5/20/13)
Smart Energy Profile (SEP) 2.0 specification released – What this means to you?
Anil Khanna (Posted 5/15/13)
When an Innovative Plan Works!
Jamie Little (Posted 5/14/13)
All Blog Posts

Valor MSS PCB Manufacturing Systems Solutions

Where Is The Manufacturing World Coming To?
Michael Ford (Posted 5/16/13)
Retain your existing investment in assembly programs even if you change your machines
Mark Laing (Posted 5/14/13)
How do you manage your assembly variants?
Mark Laing (Posted 5/8/13)
All Blog Posts

Electrical & Wire Harness Design

Estimating wiring harness costs in seconds
John Day (Posted 5/9/13)
A pickup truck with park assist and a lot more
John Day (Posted 5/6/13)
To Infinity and Beyond
J VanDomelen (Posted 4/30/13)
All Blog Posts

FPGA

OVM Gets Connected
Dennis Brophy (Posted 9/10/12)
The floating point argument
Colin Walls (Posted 9/10/12)
Open Stand & EDA Standardization
Dennis Brophy (Posted 8/28/12)
All Blog Posts

Functional Verification

Part 1: The 2012 Wilson Research Group Functional Verification Study
Harry Foster (Posted 5/8/13)
Those nasty wire’s and reg’s in Verilog
Dave Rich (Posted 5/3/13)
Getting AMP’ed Up on the IEEE Low-Power Standard
Dennis Brophy (Posted 4/29/13)
All Blog Posts

IC Design

Battle of Fins and BOXes
Arvind Narayanan (Posted 12/7/12)
TSMC 28nm yield (SemiWiki)
Simon Favre (Posted 3/5/12)
DAC 2011 is upon us!
Simon Favre (Posted 5/11/11)
All Blog Posts

Mechanical Analysis

Why Not Just Shove a Heatsink on Top of it? Part 2: Heat Flow Budgets
Robin Bornoff (Posted 5/15/13)
Why Not Just Shove a Heatsink on Top of it? Part 1
Robin Bornoff (Posted 5/13/13)
Hot Off the Press
Nazita Saye (Posted 5/3/13)
All Blog Posts

PCB Design Software & Tools

PADS Tips and Tricks: Building a PCB Decal with Polar Patterns
Jim Martens (Posted 5/13/13)
Interactive Routing in the PADS ES Suite
Jim Martens (Posted 5/9/13)
Schematic Capture in the PADS ES Suite video release
Gary Lameris (Posted 5/3/13)
All Blog Posts

System Modeling

EDA vs. Windows 8
Mike Jensen (Posted 5/6/13)
VHDL-AMS Stress Modeling – Part 3
Mike Jensen (Posted 3/25/13)
VHDL-AMS Stress Modeling - Part 2
Mike Jensen (Posted 1/28/13)
All Blog Posts

Vehicle System Design

U.S. DOT launches large V2V and V2I test
John Day (Posted 8/23/12)
Did you know this?
John Day (Posted 6/25/12)
Why aren’t tools from different suppliers easier to integrate?
John Day (Posted 6/19/12)
All Blog Posts

Aerospace and Military Solutions

To Infinity and Beyond
J VanDomelen (Posted 4/30/13)
Warp Factor 10, Mr. Sulu
J VanDomelen (Posted 4/25/13)
Bombardier Steps Up to the Big Boys
J VanDomelen (Posted 4/20/13)

Accelerating ARM-based Design

Instant Replay for Debugging SoC Level Simulations
Mark Olen (Posted 12/13/11)
GENIVI development strategy requires competitors to cooperate
John Day (Posted 11/10/11)
ARM Development Conference
Colin Walls (Posted 7/4/11)

Automotive Solutions

Estimating wiring harness costs in seconds
John Day (Posted 5/9/13)
A pickup truck with park assist and a lot more
John Day (Posted 5/6/13)
If you’re in Europe this summer
John Day (Posted 4/29/13)

Foundry Solutions

How do you define DFM?
David Abercrombie (Posted 5/19/09)
Are Design Rules Broken?
David Abercrombie (Posted 5/15/09)

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Posts tagged with 'SVRF'

Stop Paying the DRC Waiver Productivity Tax

Does SVRF Direct Read Make Sense?

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