Posted Feb 22, 2012, by Tom Fitzpatrick
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More
Tags:
Verification Methodology,
Verification Academy,
Functional Verification,
SystemC,
DVCon,
UVM Connect,
UVM-1.1,
UVM
Posted Feb 17, 2012, by Dennis Brophy
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More
Tags:
DATE Conference,
DVCon,
Accellera,
UVM,
SystemC
Posted Jan 16, 2012, by Dennis Brophy
IEEE Std. 1666™-2011 Available as Free Download
In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that … Read More
Tags:
1666-2011,
1666-2005,
TLM,
SystemC
Posted Nov 10, 2011, by Dennis Brophy
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More
Tags:
SystemC,
TLM,
Accellera,
1666,
OVM,
TLM 1.0,
TLM 2.0,
UVM,
OSCI,
Verification Academy
Posted Jun 21, 2011, by Dennis Brophy
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained … Read More
Tags:
SystemC,
TLM,
Accellera,
1666,
UVM,
OSCI,
DAC,
DATE
Posted Jun 17, 2011, by Dennis Brophy
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But … Read More
Tags:
SystemC,
Verilog,
1076.4,
1364,
1076,
VHDL,
IP-XACT,
VITAL
Posted Apr 15, 2011, by Dennis Brophy
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state … Read More
Tags:
SystemC,
esl,
1666,
OSCI,
SoC,
Jim Aynsley,
Jim Hogan
Posted Apr 1, 2011, by Thomas Bollaert
You may have already encountered the expression “Full-Chip High-Level Synthesis” on this blog. I typically define it as the ability to model, verify and synthesize complete IP subsystems starting from C++/SystemC. This obviously encompasses core processing functionality, but also control-logic, memories, hierarchy, complex interfaces and interconnects. In other words, being able to do the … Read More
Tags:
SystemC,
Full-Chip,
User Testimonial,
Catapult C,
control,
C++,
High-Level Synthesis,
Deepchip,
ESNUG,
Control-Logic Synthesis,
Cooley
Posted Feb 28, 2011, by Thomas Bollaert
This morning Intel’s Eric Lish, OSCI chair, kicked-off the North American SystemC User Group collocated at DVCon. In his presentation, Eric covered the evolution of SystemC as well as recent and upcoming milestones. It is quite remarkable to see how much effort went into developing the language and the progress made since its debuts, 12 years ago.
12 years may seem like a very long time, but … Read More
Tags:
TSMC,
SystemC,
UVM
Posted Feb 22, 2011, by Dennis Brophy
Open SystemC Initiative Tackles the Future
If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities.
For SystemC Day at … Read More
Tags:
UVM,
Jim Hogan,
NASCUG,
DVCon,
TLM,
OSCI,
SystemC
Jim Martens
John Day
J VanDomelen
Nazita Saye
Michael Ford
Robin Bornoff
Mike Jensen
Colin Walls
Patrick Carrier
Mark Laing
Zhen Mu
Travis Mikjaniec
Christopher Hallinan
Bernard Sutton