The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent objects.
In … Read More
Tags: SystemVerilog
Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More
Tags: UVM, Verification Methodology, SystemVerilog
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More
Tags: SystemVerilog, SystemC, TLM, 1800, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, Standards, IEEE-SA, UVM, OSCI, Verification Academy
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, … Read More
Tags: VHS, Verification, VIP-TSC, betamax, e, Accellera, SystemVerilog, UVM, OVM, Standards
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been … Read More
Tags: VMM, VIP-TSC, Accellera, IEEE, 1800, SystemVerilog, UVM, OVM, Standards
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained … Read More
Tags: SystemVerilog, SystemC, TLM, 1800, Accellera, 1666, UVM, IEEE, OSCI, DAC, DATE
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But … Read More
Tags: SystemVerilog, SystemC, Verilog, 1076.4, 1364, 1076, VHDL, IP-XACT, Standards, VITAL, 1800, IEEE
Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages
OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.” It is not a word I see or use much. In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825.
It struck me that the title was tending … Read More
Tags: OVM, SystemVerilog, DVCon, VHDL, Wally Rhines, UVM, Verification
This morning Intel’s Eric Lish, OSCI chair, kicked-off the North American SystemC User Group collocated at DVCon. In his presentation, Eric covered the evolution of SystemC as well as recent and upcoming milestones. It is quite remarkable to see how much effort went into developing the language and the progress made since its debuts, 12 years ago.
12 years may seem like a very long time, but … Read More
Tags: SystemVerilog, TSMC, SystemC, UVM
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi
I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi. In the last year, the IEEE announced it opened an office in Bangalore, India. This is the fourth IEEE … Read More
Tags: UPF, SystemVerilog, 1735, 1800, 1666, Standards, SystemC, 1801, IEEE-SA
Jim Martens
Harry Foster
John Day
J VanDomelen
Paul Johnston
Robin Bornoff
Mike Jensen
Colin Walls
Jay Gorajia
Mark Olen
Travis Mikjaniec
Per Viklund