Sign In
Forgot Password?
Sign In | | Create Account

Mentor Blogs

Posts tagged with 'tapeout'

15 Jan, 2014

Shelly Stalnaker DRC- and DFM-clean designs can still have hundreds to thousands of violations that must be debugged and corrected. How? Why? Mismatches between a router’s simplified tech file and the complete (and complex) signoff design rule decks at advanced nodes are generating significant numbers of DRC/DFM errors that can wreak havoc on your tapeout schedules. In particular, we’re seeing greater visibility … Read More

tech file, tapeout, DRC, Design Rule Checking, P&R, signoff, IC Design, IC Verification

15 Jan, 2014
IC Design

How Do I?

Posted by Shelly Stalnaker

Shelly Stalnaker It happens all the time, to all of us. You need a quick answer for a very specific question about using your EDA tools. You don’t want to wade through technical documentation, you don’t have time for an email response, and you really don’t want to try searching EDA forums for an answer. We feel your pain, and we decided to do something about it. Need to know how to extract a net from … Read More

tapeout, Debugging, Calibre, Productivity, signoff, electrical verification, Physical Verification

13 Dec, 2013
IC Design

Qualification Is Just the Beginning

Posted by Shelly Stalnaker

Shelly Stalnaker Press releases can make it seem like EDA tool qualification for a particular IC process node is the “end game.” But in truth, qualification is just the first publicly visible step of ongoing collaborations between an EDA vendor and the foundry. Michael White takes you behind the curtain for a peek at what goes on during qualification from start to finish, as part of his ongoing Silicon Edge series … Read More

tool qualification, tapeout, DRM, Foundry, design rule manual, process design kit, rule deck, IC, PDK

13 Dec, 2013

Shelly Stalnaker Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More

DRC, digital IC, Foundry, tech files, tapeout, 14nm, rule decks, signoff, 16nm, SoC, 10nm, SVRF, IP, Design Rule Checking, P&R, router, 20nm, Routing, Debugging

13 Dec, 2013

Shelly Stalnaker The need for high reliability covers a wide array of market segments, all with differing acceptance requirements. In this video, Matt Hogan explores the challenges of comprehensive reliability verification, and demonstrates how Calibre PERC can help you satisfy the most demanding requirements with confidence. … Read More

ERC, PERC, Calibre, reliability verification, tapeout

Embedded Software

PADS Home Page

PCB Design

Valor PCB Manufacturing Systems Solutions

Electrical & Wire Harness Design

Functional Verification

IC Manufacturing

IC Design

Mechanical Analysis

Silicon Test and Yield Analysis

System Modeling

Vehicle System Design

3D-IC Design and Test Solutions

Aerospace and Military Solutions

Accelerating ARM-based Design

Automotive Solutions

Fabless/Foundry Ecosystem Solutions

Recent Comments