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Posts tagged with 'Thermal Headroom'

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Mind Your Head(room) Again

Posted Nov 13, 2009, by John Parry

Thermal headroom is a concept I’ve been pushing for a few years, but I guess many people aren’t familiar with it, so I thought some additional commentary would be appropriate. Here goes: What I’ve drawn looks pretty simple. Starting from the ambient we can attribute to total temperature rise for some critical IC to a temperature rise in the air, the PCB and/or heat sink, then the temperature rise in … Read More

Tags: Thermal Management, Thermal Headroom, Design Flow, Design Process, CFD, FloTHERM.PACK, Thermal Design, FloEFD

Mechanical Analysis

Mind Your Head(room)

Posted Nov 4, 2009, by John Parry

In “What’s black and stuck on a PCB?” I promised I’d get back to writing about FloTHERM.PACK and how it can really help your thermal modelling by helping you build accurate thermal models of chip packages. Assuming you’ve been using FloTHERM or FloTHERM.PCB without FloTHERM.PACK I guess I first need convince you about why you should bother. To help me do that I’d like to introduce you to the concept … Read More

Tags: Thermal Model, DELPHI Model, 2-Resistor Model, IC Packaging, Thermal Headroom, FloTHERM.PACK, FloTHERM.PCB

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ebay said Hello, just wanted to mention, I liked this post. ... in DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
Roger said I do have to agree. Learning to be computer engien... in X-Ray Vision Glasses … Here and Now
Mutlu said Hi John,Thanks for the comment.I think you and I a... in UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
Dave Rich said Make sure you are using the 32-bit version of Ques... in Using the UVM 1.0 Release with Questa
BK said How to resolve error in simulating UVM1.1 W7(64-bi... in Using the UVM 1.0 Release with Questa
(Wasted) Effort Spent In Verification | AgileSoC said [...] in that series comes via my new favorite har... in Part 5: The 2010 Wilson Research Group Functional Verification Study
(Wasted) Effort Spent In Verification | AgileSoC said [...] just spent a few minutes reading Harry Foste... in Prologue: The 2010 Wilson Research Group Functional Verification Study
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omer said Hello Dave, Thank you very much for progressive e... in SystemVerilog Coding Guidelines: Package import versus `include
Michael Ford said The currently most popular aspect of design for re... in Extreme Design!

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