I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield:
“I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, … Read More
One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL.
Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new … Read More
Tags: Vista, DAC, esl, Catapult C, TSMC, Verification, High-Level Synthesis, How-to
This morning Intel’s Eric Lish, OSCI chair, kicked-off the North American SystemC User Group collocated at DVCon. In his presentation, Eric covered the evolution of SystemC as well as recent and upcoming milestones. It is quite remarkable to see how much effort went into developing the language and the progress made since its debuts, 12 years ago.
12 years may seem like a very long time, but … Read More
Jim Martens
John Day
J VanDomelen
Nazita Saye
Michael Ford
Robin Bornoff
Mike Jensen
Colin Walls
Tom Fitzpatrick
Patrick Carrier
Mark Laing
Zhen Mu
Travis Mikjaniec
Christopher Hallinan
Bernard Sutton