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Mentor Blogs

Posts tagged with 'Universal Verification Methodology'

23 Feb, 2014

Dennis Brophy UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest.  It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon. The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of … Read More

DVClub, DVCon, Accellera, Universal Verification Methodology, UVM 1.2, Git, OSCI

22 Feb, 2011

J VanDomelen The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More

UVM, Universal Verification Methodology, Milaero, Open Verification Methodology, OVM, TSC, Accellera, Mentor, IC, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP

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