Sign In
Forgot Password?
Sign In | | Create Account

Mentor Blogs

Posts tagged with 'UVM-1.0'

28 Jun, 2010

Mark Glasser Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  … Read More

OVM, UVM, Accellera, UVM-1.0, VIP-TSC, UVM E.A., UVM Early Adopter

PADS Home Page

PCB Design

Valor PCB Manufacturing Systems Solutions

Electrical & Wire Harness Design

Functional Verification

IC Manufacturing

IC Design

Mechanical Analysis

Silicon Test and Yield Analysis

System Modeling

Vehicle System Design

3D-IC Design and Test Solutions

Aerospace and Military Solutions

Accelerating ARM-based Design

Automotive Solutions

Fabless/Foundry Ecosystem Solutions

Recent Comments