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Posts tagged with 'UVM'

16 Oct, 2012

Dennis Brophy A new style takes center stage It was Fashion Week in Portland, Oregon in early October.  And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was.  What struck me was the blend of fashion with high tech this year.  Intel took the opportunity to roll out its fashion inspired campaign (dressing … Read More

UVM, UVM Cookbook, OVM, Verification, Verification Academy

20 Jul, 2012

Dennis Brophy Live & In-Person at DAC 2012! Verification Academy, the brain child of Dr. Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year.  Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor. The Verification Academy, predominantly a web-based resource is a popular … Read More

Formal, Doulos, Verification Academy, UVM Express, Verification Trends, Tech Design Forum, ACE, Thales, AMS, UPF, ABV, UVM, Coverage Closure, iTBA, DAC, Low Power, ARM, OVM, Assertion-Based Verification

16 Jul, 2012

Dennis Brophy Open-Source Proof-of-Concept Library Released Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011.  The completed and published standard was made available to the community … Read More

UVM, Accellera Systems Initiative, 1666, SystemC, open-source, proof-of-concept library

30 May, 2012
Functional Verification

Off to DAC!

Posted by Dennis Brophy

Dennis Brophy Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC).  If you happen to like some of the same events I attend, then the chances are good our paths might cross in public. Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.  Split across two days, Accellera board members will meet to conduct traditional … Read More

UPF, UCIS, UVM, DAC, EDAC, Accellera, Verification Academy, SystemC, TLM, Gary Smith

26 Feb, 2012

Harry Foster The philosophy behind our Verification Academy is to provide a comprehensive resource for evolving and maturing your functional verification process skills. We believe that each step an organization takes in evolving verification skills should have measurable results and benefits. With that in mind, I am excited to announce two new modules we are adding to the Verification Academy: UVM Express and Advanced … Read More

Verification Academy, UVM

22 Feb, 2012

Tom Fitzpatrick In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More

Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM

21 Feb, 2012
Functional Verification

Tornado Alert!!!

Posted by Dennis Brophy

Dennis Brophy Is my car trying to tell me something? This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More

UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM

17 Feb, 2012

Dennis Brophy It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More

DATE Conference, DVCon, Accellera, UVM, SystemC

11 Nov, 2011

Dave Rich Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More

UVM, Verification Methodology

10 Nov, 2011

Dennis Brophy IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More

SystemC, TLM, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, UVM, OSCI, Verification Academy

13 Oct, 2011
Functional Verification

VHS or Betamax?

Posted by Dennis Brophy

Dennis Brophy Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

5 Oct, 2011

Dennis Brophy Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs.  The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011). Harry has been … Read More

VMM, VIP-TSC, Accellera, UVM, OVM

22 Jul, 2011

Dennis Brophy Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase.  New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it.  Everyone had their favorite VHDL book and I … Read More

VITAL, VHDL, VMM, OVM, Accellera, UVM, UVM World, OVM World

24 Jun, 2011

Tom Fitzpatrick Well, another DAC is behind us, and you know what that means. That’s right, the super-sized DAC issue of Verification Horizons is now available online. You can download the full issue or individual articles from the Verification Horizons tab at Verification Academy. Over the next few days, I’ll be highlighting some of the articles to give you a taste of the great content available directly … Read More

UVM, Verification Academy, Functional Verification, Verification Horizons

21 Jun, 2011

Dennis Brophy System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here. While this may come as a surprise to many, one thing has remained constant … Read More

SystemC, TLM, Accellera, 1666, UVM, OSCI, DAC, DATE

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