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Mentor Blogs

Posts tagged with 'UVM'

22 Feb, 2012

Tom Fitzpatrick In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More

Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM

21 Feb, 2012
Functional Verification

Tornado Alert!!!

Posted by Dennis Brophy

Dennis Brophy Is my car trying to tell me something? This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology … Read More

UVM, Tipping Point, Veloce, inFact, Intelligent Testbench Automation, Crossing the Chasam, Questa, SoC, iTBA, OVM

17 Feb, 2012

Dennis Brophy It is time to talk about what happens next with UVM The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference … Read More

DATE Conference, DVCon, Accellera, UVM, SystemC

11 Nov, 2011

Dave Rich Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More

UVM, Verification Methodology

10 Nov, 2011

Dennis Brophy IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature … Read More

SystemC, TLM, Accellera, 1666, OVM, TLM 1.0, TLM 2.0, UVM, OSCI, Verification Academy

13 Oct, 2011
Functional Verification

VHS or Betamax?

Posted by Dennis Brophy

Dennis Brophy Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

5 Oct, 2011

Dennis Brophy Is Legacy Holding You Back? Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs.  The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011). Harry has been … Read More

VMM, VIP-TSC, Accellera, UVM, OVM

22 Jul, 2011

Dennis Brophy Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase.  New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it.  Everyone had their favorite VHDL book and I … Read More

VITAL, VHDL, VMM, OVM, Accellera, UVM, UVM World, OVM World

24 Jun, 2011

Tom Fitzpatrick Well, another DAC is behind us, and you know what that means. That’s right, the super-sized DAC issue of Verification Horizons is now available online. You can download the full issue or individual articles from the Verification Horizons tab at Verification Academy. Over the next few days, I’ll be highlighting some of the articles to give you a taste of the great content available directly … Read More

UVM, Verification Academy, Functional Verification, Verification Horizons

21 Jun, 2011

Dennis Brophy System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here. While this may come as a surprise to many, one thing has remained constant … Read More

SystemC, TLM, Accellera, 1666, UVM, OSCI, DAC, DATE

21 Apr, 2011

Dennis Brophy User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free.  U2U … Read More

Functional Verification, OVM, Accellera, UVM, VIP, U2U

25 Mar, 2011

Dennis Brophy Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

22 Feb, 2011

J VanDomelen The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More

UVM, Universal Verification Methodology, Milaero, Open Verification Methodology, OVM, TSC, Accellera, Mentor, IC, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP

22 Feb, 2011

Dennis Brophy Open SystemC Initiative Tackles the Future If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM).  And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days.  But you may also want to bring a colleague to attend the SystemC Day activities. For SystemC Day at DVCon, … Read More

UVM, Jim Hogan, NASCUG, DVCon, TLM, OSCI, SystemC

28 Jan, 2011

Dennis Brophy Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.  With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support for … Read More

UVM, DVCon, EDSFair, Accellera, OVM, SCE-MI

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