Historical Perspective In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and I … Read More
Posts tagged with 'UVM'
Well, another DAC is behind us, and you know what that means. That’s right, the super-sized DAC issue of Verification Horizons is now available online. You can download the full issue or individual articles from the Verification Horizons tab at Verification Academy. Over the next few days, I’ll be highlighting some of the articles to give you a taste of the great content available directly … Read More
System Standards Worlds Initiate Unification Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here. While this may come as a surprise to many, one thing has remained constant … Read More
User Adoption of OVM Featured; Views on UVM Discussed The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set. U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens. Registration for the event is open and is fee-free. U2U … Read More
Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.” It is not a word I see or use much. In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More
The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More
UVM, Universal Verification Methodology, Milaero, Design Automation, Open Verification Methodology, OVM, TSC, Accellera, Mentor, IC, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP
Open SystemC Initiative Tackles the Future If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities. For SystemC Day at DVCon, … Read More
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology. With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa. The major addition to SCE-MI 2.1 is support for … Read More
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James. The goal of verification planning … Read More
23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway. While the Accellera VIP-TSC is making good progress, limited information is available to non-participants. This limited knowledge is true for … Read More
Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC). Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate. As … Read More
Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements. Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently. Further, as part of the Accellera VIP-TSC UVM development … Read More
Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM? The answer depends a lot on where you are in code development and what your risk tolerance is. The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet. It will be around for a long time. … Read More
DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement can be read at EDA Cafe, click here. The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology … Read More
Visit Booth 1383 – The hub of OVM/UVM Activity at DAC The OVM World booth at the Design Automation Conference (#1383) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from 4:30 p.m. to 6:00 p.m. The Open Verification Methodology (OVM) is the industry’s open and interoperable solution, guaranteed to run on … Read More
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