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Mentor Blogs

Posts tagged with 'Verification'

15 Jul, 2013

Harry Foster   Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of the amount of effort spent in verification. Directly asking study participants … Read More

Functional Verification, Accellera, Verification Academy, Verification Methodology, Verification

28 Jun, 2013

Harry Foster Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends. Independent Asynchronous Clock Domains Figure 1 shows the percentage … Read More

Verification Academy, Verification, Verification Methodology, Functional Verification, Accellera, Wilson Research Group Study, UPF, IEEE 1801, Low Power

8 May, 2013

Harry Foster  Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.  This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing … Read More

Functional Verification, Accellera, Verification Academy, IEEE 1800, Verification

3 May, 2013

Dave Rich A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog … Read More

Verification, Functional Verification, Verilog

7 Feb, 2013

Dave Rich The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the presses; though I doubt people will be printing the 1300+ pages on their own from the soon to be readily available online version. Here’s a little background into what’s in all those pages. The first SystemVerilog LRM came from Accellera in 2002 as a set of extensions to the IEEE 1364-2001 … Read More

functional coverage, Constrained Random Test, Verification

16 Oct, 2012

Dennis Brophy A new style takes center stage It was Fashion Week in Portland, Oregon in early October.  And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was.  What struck me was the blend of fashion with high tech this year.  Intel took the opportunity to roll out its fashion inspired campaign (dressing … Read More

UVM, UVM Cookbook, OVM, Verification, Verification Academy

26 Jul, 2012

Mark Olen A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables … Read More

Functional Verification, Instant Replay, Emulation, Verification, Verification Academy, JTAG, SoC

13 Dec, 2011

Mark Olen

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing multiple replays of events in question

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Verification, testbench, SoC Level Verification, Cortex, ARM, Software as a Testbench, Functional Verification, SoC

13 Oct, 2011
Functional Verification

VHS or Betamax?

Posted by Dennis Brophy

Dennis Brophy Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

26 Jul, 2011

Mark Olen Who Doesn’t Like Faster? In my last blog post I introduced new technology called Intelligent Testbench Automation (“iTBA”).  It’s generating lots of interest in the industry because just like constrained random testing (“CRT”), it can generate tons of tests for functional verification.  But it has unique efficiencies that allow you to achieve coverage 10X to 100X … Read More

Functional Verification, Intelligent Testbench Automation, Constrained Random Test, testbench, Verification, iTBA

28 Jun, 2011

Mark Olen iTBA Introduction If you’ve been to DAC or DVCon during the past couple of years, you’ve probably at least heard of something new called “Intelligent Testbench Automation”.  Well, it’s actually not really all that new, as the underlying principles have been used in compiler testing and some types of software testing for the past three decades, but its application to electronic design verification is … Read More

Functional Verification, Intelligent Testbench Automation, functional coverage, Verification, Verification Academy, testbench

20 Apr, 2011

Harry Foster Testbench Characteristics and Simulation Strategies (Continued) This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 6 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation … Read More

testbench, Functional Verification, Verification

18 Apr, 2011

Harry Foster Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. In this blog, I focus on some of the 2010 Wilson Research Group … Read More

testbench, Functional Verification, Verification, Wilson Research Group Study

4 Apr, 2011

Harry Foster   Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues this discussion. I stated in my previous blog … Read More

Functional Verification, Verification, Formal Verification

3 Apr, 2011

Harry Foster   Effort Spent On Verification This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of amount of effort spent in verification. I have been on the technical program … Read More

Functional Verification, Verification, Add new tag

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