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Mentor Blogs

Posts tagged with 'Verification'

16 Oct, 2012

Dennis Brophy A new style takes center stage It was Fashion Week in Portland, Oregon in early October.  And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was.  What struck me was the blend of fashion with high tech this year.  Intel took the opportunity to roll out its fashion inspired campaign (dressing … Read More

UVM, UVM Cookbook, OVM, Verification, Verification Academy

26 Jul, 2012

Mark Olen A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables … Read More

Functional Verification, Instant Replay, Emulation, Verification, Verification Academy, JTAG, SoC

13 Dec, 2011

Mark Olen

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing multiple replays of events in question

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Verification, testbench, SoC Level Verification, Cortex, ARM, Software as a Testbench, Functional Verification, SoC

13 Oct, 2011
Functional Verification

VHS or Betamax?

Posted by Dennis Brophy

Dennis Brophy Legacy’s Luster Lost As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole. Buy why this title?  For some, … Read More

VHS, Verification, VIP-TSC, betamax, e, Accellera, UVM, OVM

26 Jul, 2011

Mark Olen Who Doesn’t Like Faster? In my last blog post I introduced new technology called Intelligent Testbench Automation (“iTBA”).  It’s generating lots of interest in the industry because just like constrained random testing (“CRT”), it can generate tons of tests for functional verification.  But it has unique efficiencies that allow you to achieve coverage 10X to 100X … Read More

Functional Verification, Intelligent Testbench Automation, Constrained Random Test, testbench, Verification, iTBA

28 Jun, 2011

Mark Olen iTBA Introduction If you’ve been to DAC or DVCon during the past couple of years, you’ve probably at least heard of something new called “Intelligent Testbench Automation”.  Well, it’s actually not really all that new, as the underlying principles have been used in compiler testing and some types of software testing for the past three decades, but its application to electronic design verification is … Read More

Functional Verification, Intelligent Testbench Automation, functional coverage, Verification, Verification Academy, testbench

20 Apr, 2011

Harry Foster Testbench Characteristics and Simulation Strategies (Continued) This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 6 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation … Read More

testbench, Functional Verification, Verification

18 Apr, 2011

Harry Foster Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. In this blog, I focus on some of the 2010 Wilson Research Group … Read More

testbench, Functional Verification, Verification, Wilson Research Group Study

4 Apr, 2011

Harry Foster   Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues this discussion. I stated in my previous blog … Read More

Functional Verification, Verification, Formal Verification

3 Apr, 2011

Harry Foster   Effort Spent On Verification This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of amount of effort spent in verification. I have been on the technical program … Read More

Functional Verification, Verification, Add new tag

1 Apr, 2011

Harry Foster   Reuse Trends This blog is a continuation of a series of blogs, which presents the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I focus on design and verification reuse trends. Design Composition Trends Figure 1 shows the mean design composition trends, which compares the 2007 Far West Research study (in blue) with  the 2010 Wilson Research … Read More

Verification, Functional Verification

31 Mar, 2011

Harry Foster Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified by the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on embedded processor, power management, and clock domain trends. Embedded Processors In Figure 1, we see the percentage … Read More

Verification, Functional Verification

30 Mar, 2011

Harry Foster   In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the electronic industry’s state and trends in design and verification at that point in time. However, after the 2004 study, no other industry studies were conducted, which left a void in indentifying industry trends. To address this void, … Read More

Verification, Functional Verification

25 Mar, 2011

Dennis Brophy Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

10 Feb, 2011

Matthew Hogan Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks. Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need … Read More

Low Power, PERC, ERC, thin oxide, Verification

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