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Mentor Blogs

Posts tagged with 'Verification'

1 Apr, 2011

Harry Foster   Reuse Trends This blog is a continuation of a series of blogs, which presents the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I focus on design and verification reuse trends. Design Composition Trends Figure 1 shows the mean design composition trends, which compares the 2007 Far West Research study (in blue) with  the 2010 Wilson Research … Read More

Verification, Functional Verification

31 Mar, 2011

Harry Foster Design Trends (Continued) In Part 1 of this series of blogs, I focused on design trends (click here) as identified by the 2010 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on embedded processor, power management, and clock domain trends. Embedded Processors In Figure 1, we see the percentage … Read More

Verification, Functional Verification

30 Mar, 2011

Harry Foster   In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the electronic industry’s state and trends in design and verification at that point in time. However, after the 2004 study, no other industry studies were conducted, which left a void in indentifying industry trends. To address this void, … Read More

Verification, Functional Verification

25 Mar, 2011

Dennis Brophy Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.”  It is not a word I see or use much.  In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825. It struck me that the title was tending … Read More

OVM, DVCon, VHDL, Wally Rhines, UVM, Verification

10 Feb, 2011

Matthew Hogan Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks. Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need … Read More

Low Power, PERC, ERC, thin oxide, Verification

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