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Mentor Blogs

Posts tagged with 'Verification Methodology'

12 Aug, 2013

Harry Foster Language and Library Trends (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (Part 8 click here), I focused on design and verification language trends, as identified by the Wilson Research Group study. This blog presents additional … Read More

SVA, UVM, Accellera, Assertion-Based Verification, Verification Methodology, OVL, PSL, Functional Verification

26 Jul, 2013

Mark Olen You don’t need a graphic like the one below to know that multi-core SoC designs are here to stay.  This one happens to be based on ARM’s AMBA 4 ACE architecture which is particularly effective for mobile design applications, offering an optimized mix of high performance processing and low power consumption.  But with software’s increasing role in overall design functionality, verification engineers … Read More

Intelligent Testbench Automation, iTBA, Emulation, Verification Academy, Verification Methodology, Verification

22 Jul, 2013

Harry Foster Effort Spent On Verification (Continued) This blog is a continuation of a series of blogs that present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here). In my previous blog (click here), I focused on the controversial topic of effort spent in verification. This blog continues that discussion. I stated in my previous blog that … Read More

Verification Academy, Verification, Verification Methodology, Formal Verification, Functional Verification, Accellera, UVM, IEEE 1800

15 Jul, 2013

Harry Foster   Effort Spent in Verification This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on design and verification reuse trends. In this blog, I focus on the controversial topic of the amount of effort spent in verification. Directly asking study participants … Read More

Functional Verification, Accellera, Verification Academy, Verification Methodology, Verification

8 Jul, 2013

Harry Foster Reuse Trends This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on clocking and power management.  In this blog, I focus on design and verification reuse trends. As I mentioned in my prologue blog to this series (click here), one interesting trend that … Read More

Functional Verification, Reuse, Formal Verification, Verification Academy, Verification Methodology

28 Jun, 2013

Harry Foster Clocking and Power Trends In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends. Independent Asynchronous Clock Domains Figure 1 shows the percentage … Read More

Verification Academy, Verification, Verification Methodology, Functional Verification, Accellera, Wilson Research Group Study, UPF, IEEE 1801, Low Power

23 Apr, 2013

Harry Foster This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

22 Feb, 2012

Tom Fitzpatrick In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this … Read More

Verification Methodology, Verification Academy, Functional Verification, SystemC, DVCon, UVM Connect, UVM-1.1, UVM

11 Nov, 2011

Dave Rich Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a few Object-Oriented programming principals so you can extend a UVM class into something for … Read More

UVM, Verification Methodology

3 Dec, 2010

Harry Foster As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce a new module focused on Verification Planning, which has been one of the Verification Academy’s most-requested subjects for new content. The new Verification Planning module is delivered by our subject matter expert, who literally wrote the book on the subject, Peet James. The goal of verification planning … Read More

Functional Verification, OVM, Assertion-Based Verification, Verification Methodology, UVM, Verification Academy

10 Sep, 2010

Dennis Brophy Companion OVM Cookbook Examples Kit also offered for download Several months ago, the OVM Cookbook and the Examples Kit were made available for online use at the Verification Academy.  This proved to be a great help to accelerate the skill level of new OVM users.  Given the number of new projects that have deployed OVM and the number of new engineers that now need to use OVM, there is increased demand … Read More

OVM, Verification Academy, cookbook, Verification Methodology

21 May, 2010

Dennis Brophy Easier DUT to Testbench Connections This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench.  The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA. This extension also introduces the dual top methodology. This methodology isolates the connections between the … Read More

UVM, Verification Methodology, Accellera

8 Apr, 2010

Dennis Brophy Companion UVM-EA OVM Compatibility Overlay Kit for Available for Download Mentor Graphics has made available its UVM-EA starter kit to promote OVM users’ feedback on UVM. As I wrote in an earlier blog, Accellera has defined specific modifications to OVM 2.1.1 to create UVM-EA.  The Mentor Graphics version of the UVM-EA can be downloaded here.  The UVM-EA starter kits passes all our Questa 6.6 regression … Read More

UVM Early Adopter, Verification Methodology, Interoperability, OVM, Accellera, UVM, UVM E.A.

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