Mentor Blogs

A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog … Read More

Verification, Functional Verification, Verilog

This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the … Read More

UVM, Assertion-Based Verification, Formal Verification, Accellera, Verification Academy, Verification Methodology, functional coverage, Verilog, Functional Verification, VHDL

In the early days of embedded systems, software engineers typically had some understanding of hardware design. Indeed, in many cases, it was the hardware designer who implemented the software. Over the years, as the amount of software development has increased, engineers have become less and less “hardware aware”. I find this transition interesting from the viewpoint of an embedded software … Read More

Verilog, RTOS, VHDL, FPGA, MicroBlaze, NIOS, Nucleus

Some weeks ago, I published a posting from my colleague Richard Vlamynck, who was explaining the ideas behind System-C and modeling at different levels of abstraction. He promised to write more and I was very pleased to receive a new contribution … It’s just me again, blogging about hardware models in general and System-C in particular. Earlier, I’d mentioned the fact that System-C can be used … Read More

VHDL, System-C, Precision, Handel-C, Verilog

As I work for a company that has traditionally had a strong focus on hardware design, I am particularly interested in the relationship between hardware and software development and the synergies between the two disciplines. Previously, I have discussed the dominance of software in modern designs [here] and the relationships in the EDA world [here]. But today I want to think about how hardware guys … Read More

Hardware, Verilog, VHDL, hardware design

How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But … Read More

SystemC, Verilog, 1076.4, 1364, 1076, VHDL, IP-XACT, VITAL

United States Plays Host in Seattle, WA The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA.  Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered.  Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working … Read More

1364, 1666, 1076, iec, TC93, Verilog, VHDL, dual-logo, WG2

Just in time for the holidays!  IEEE Std. 1800™-2009, aka SystemVerilog 2009, is ready for purchase and download from the IEEE.  The standard was developed by the SystemVerilog Working Group and recently approved by the IEEE.  It is an entity project of the IEEE jointly sponsored by the Corporate Advisory Group (CAG) and the Design Automation Standards Committee (DASC).  The working group members … Read More

CAG, 1364, Verilog, PLI, VPI, DASC, DPI

Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future… Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout … Read More

Verilog, SPICE, Calibre_LVS, Hierarchical LVS, Calibre, Netlist, nmLVS, Hierarchical_LVS, LVS